SLLSFZ7 February   2025 TUSB1146-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.2
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration In I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Linear EQ Configuration
      5. 6.4.5 Linearity VOD
      6. 6.4.6 VOD Modes
        1. 6.4.6.1 Linearity VOD
        2. 6.4.6.2 Limited VOD
      7. 6.4.7 Transmit Equalization
      8. 6.4.8 USB3.2 Modes
      9. 6.4.9 Downstream Facing Port Adaptive Equalization
        1. 6.4.9.1 Fast Adaptive Equalization in I2C Mode
        2. 6.4.9.2 Full Adaptive Equalization
        3. 6.4.9.3 Full Adaptive Equalization in GPIO Mode (I2C_EN = "F")
    5. 6.5 Programming
      1. 6.5.1 Transition Between Modes
      2. 6.5.2 Pseudocode Examples
        1. 6.5.2.1 Fast AEQ With Linear Redriver Mode
        2. 6.5.2.2 Fast AEQ With Limited Redriver Mode
        3. 6.5.2.3 Full AEQ With Linear Redriver Mode
        4. 6.5.2.4 Full AEQ With Limited Redriver Mode
      3. 6.5.3 TUSB1146-Q1 I2C Address Options
      4. 6.5.4 TUSB1146-Q1 I2C Target Behavior
  9. 7 Register Maps
    1. 7.1 TUSB1146-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C Receptacle) Configuration
        2. 8.2.2.2 USB Downstream Facing Port (USB-C Receptacle to USB Host) Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Fast Adaptive Equalization
          3. 8.2.2.2.3 Full Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2-Lane DisplayPort Mode
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 USB and DP Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
USB Gen 2 Differential Receiver (RX1p/n, RX2p/n, SSTXp/n)
V(RX-DIFF-PP) Input differential peak-peak voltage swing linear dynamic range AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel 1200 mVppd
V(RX-DC-CM) Common-mode voltage bias in the receiver (DC) 0 V
VRX_CM-INST Maximum instantaneous RX DC common-mode voltage change for following operating states: OFF to ON, Disabled to Disconnect, U3 to Disconnect. Measured at non-redriver side of AC-coupling capacitor with 200kΩ load. –500   1000 mV
VRX_CM-INST Maximum instantaneous RX DC common-mode voltage change for following operating states: Disconnect to U0, U0 to U3, U3 to U0. Measured at non-redriver side of AC-coupling capacitor with 50Ω load. –300   1000 mV
R(RX-DIFF-DC) Differential input impedance (DC) Present after a USB3 device is detected on TXP/TXN 72 90 120 Ω
R(RX-CM-DC) Receiver DC common-mode impedance Present after a USB3 device is detected on TXP/TXN 18 30 Ω
Z(RX-HIGH-IMP-DC-POS) Common-mode input impedance with termination disabled (DC) Present when no USB3 device is detected on TXP/TXN. Measured over the range of 0V to 500mV with respect to GND. 25 kΩ
V(SIGNAL-DET-DIFF-PP) Input differential peak-to-peak signal detect assert level At 10Gbps, no input loss, PRBS7 pattern 90 mVppd
V(RX-IDLE-DET-DIFF-PP) Input differential peak-to-peak signal detect deassert level At 10Gbps, no input loss, PRBS7 pattern 70 mVppd
V(RX-LFPS-DET-DIFF-PP) Low frequency periodic signaling (LFPS) detect threshold VCC = 3.3V; 25℃ ≤ TA ≤ 105℃; Tested at 25MHz and 300mVppd VIN; Below the minimum is squelched 100 300 mVppd
V(RX-CM-AC-P) Peak RX AC common-mode voltage Measured at package pin 150 mVppd
RL(RX-DIFF) Differential return loss 50MHz to 1.25GHz at 90Ω; –19 dB
RL(RX-DIFF) Differential return loss 5GHz at 90Ω; –7 dB
RL(RX-CM) Common-mode return loss 50MHz to 5GHz at 90Ω; –7 dB
EQ_SSTX0 SSTX Receiver equalization at 100MHz FLIPSEL = 0; SSEQ_SEL = 0; 1.8 dB
EQ_SSTX0 SSTX Receiver equalization at 100MHz FLIPSEL = 1; SSEQ_SEL = 0; 2.1 dB
EQ_SSTX15 SSTX Receiver equalization at 100MHz FLIPSEL = 0; SSEQ_SEL = 15; 3.6 dB
EQ_SSTX15 SSTX Receiver equalization at 100MHz FLIPSEL = 1; SSEQ_SEL = 15; 4.0 dB
EQ_SSTX15 SSTX Receiver equalization at 2.5GHz FLIPSEL = 0; SSEQ_SEL = 15; 12.0 dB
EQ_SSTX15 SSTX Receiver equalization at 2.5GHz FLIPSEL = 1; SSEQ_SEL = 15; 12.2 dB
EQ_SSTX15 SSTX Receiver equalization at 5GHz FLIPSEL = 0; SSEQ_SEL = 15; 14.5 dB
EQ_SSTX15 SSTX Receiver equalization at 5GHz FLIPSEL = 1; SSEQ_SEL = 15; 14.5 dB
EQ_RX0 RX1 Receiver equalization at 100MHz FLIPSEL = 0; EQ1_SEL = 0; 1.7 dB
EQ_RX15 RX1 Receiver equalization at 100MHz FLIPSEL = 0; EQ1_SEL = 15; 3.5 dB
EQ_RX15 RX1 Receiver equalization at 2.5GHz FLIPSEL = 0; EQ1_SEL = 15; 11.6 dB
EQ_RX15 RX1 Receiver equalization at 5GHz FLIPSEL = 0; EQ1_SEL = 15; 14.1 dB
EQ_RX0 RX2 Receiver equalization at 100MHz FLIPSEL = 1; EQ2_SEL = 0; 2.0 dB
EQ_RX15 RX2 Receiver equalization at 100MHz FLIPSEL = 1; EQ2_SEL = 15; 3.8 dB
EQ_RX15 RX2 Receiver equalization at 2.5GHz FLIPSEL = 1; EQ2_SEL = 15; 11.4 dB
EQ_RX15 RX2 Receiver equalization at 5GHz FLIPSEL = 1; EQ2_SEL = 15; 13.4 dB
CAC-USB1 Required external AC-coupling capacitor on SSTX 75 265 nF
CAC-USB2 Optional external AC-coupling capacitor on RX1 and RX2. 297 363 nF
USB Gen 2 Differential Transmitter (TX1p/n, TX2p/n, SSRXp/n)
VTX(DIFF-PP) Transmitter dynamic differential voltage swing range. 1200 mVppd
VTX(RCV-DETECT) Amount of voltage change allowed during receiver detection At TA = 25℃; 600 mV
VTX-CM-INST Max Instantaneous TX DC common-mode voltage change under following operating states:  OFF to ON, ON to OFF, Disabled to Disconnect, U3 to Disconnect. Measured single-ended at non-redriver side of AC-coupling capacitor with 200kΩ load. –500   1000 mV
VTX-CM-INST Max Instantaneous TX DC common-mode voltage change under following operating states:  Disconnect to U0, U0 to U2/U3, U2/U3 to U0. Measured single-ended at non-redriver side of AC-coupling capacitor with 50Ω load. –300   1000 mV
VTX(CM-IDLE-DELTA) Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS –300 600 mV
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC) 0.5 1.1 V
VTX(CM-AC-PP-ACTIVE) Tx AC common-mode voltage active Max mismatch from Txp + Txn for both time and amplitude 100 mVpp
VTX(IDLE-DIFF-AC-PP) AC electrical idle differential peak-to-peak output voltage At package pins after high-pass filter (HPF) to remove DC component; HPF = 1/LPF; No AC or DC signals are applied at RX terminals; 0 10 mV
VTX(IDLE-DIFF-DC) DC electrical idle differential output voltage At package pins after low-pass filter (LPF) to remove AC component; LPF = 1/HPF; No AC or DC signals are applied at RX terminals; 0 14 mV
VTX(CM-DC-ACTIVE-IDLE-DELTA) Absolute DC common-mode voltage between U1 and U0 At package pin 200 mV
RTX(DIFF) Differential impedance of the driver 72 90 120 Ω
RTX(CM) Common-mode impedance of the driver Measured with respect to AC ground over
0V to 500mV		 18 30 Ω
VSSRX-LIMITED-VODL0 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L0 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 725 mVppd
VSSRX-LIMITED-VODL1 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L1 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 850 mVppd
VSSRX-LIMITED-VODL2 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L2 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 1000 mVppd
VSSRX-LIMITED-VODL3 SSRX differential peak-to-peak voltage when configured for limited redriver and LINR_L3 TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 0; 1100 mVppd
VSSRX-DE-RATIO0 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b00; USB_SSRX_VOD = 2'b00 (LINR_L3); –1.5 dB
VSSRX-DE-RATIO1 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b01;  USB_SSRX_VOD = 2'b00 (LINR_L3); –2.1 dB
VSSRX-DE-RATIO2 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b10;  USB_SSRX_VOD = 2'b00 (LINR_L3); –3.2 dB
VSSRX-DE-RATIO3 SSRX de-emphasis when configured for limited redriver and de-emphasis enabled. TX_PRESHOOT_EN = 0; TX_DEEMPHASIS_EN = 1; TX_DEEPHASIS = 2'b11;  USB_SSRX_VOD = 2'b00 (LINR_L3); –3.8 dB
VSSRX-PRESH-RATIO0 SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b00;  USB_SSRX_VOD = 2'b00 (LINR_L3); 1.5 dB
VSSRX-PRESH-RATIO1 SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b01;  USB_SSRX_VOD = 2'b00 (LINR_L3); 2.0 dB
VSSRX-PRESH-RATIO2 SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b10;  USB_SSRX_VOD = 2'b00 (LINR_L3); 2.3 dB
VSSRX-PRESH-RATIO3 SSRX pre-shoot level when configured for limited redriver and pre-shoot enabled. TX_PRESHOOT_EN = 1; TX_DEEMPHASIS_EN = 0; TX_PRESHOOT = 2'b11;  USB_SSRX_VOD = 2'b00 (LINR_L3); 2.8 dB
ITX(SHORT) TX short circuit current TX± shorted to GND 40 mA
RLTX(DIFF) Differential return loss 50MHz to 1.25GHz at 90Ω –20 dB
RLTX(DIFF) Differential return loss 5GHz at 90Ω –13 dB
RLTX(CM) Common-mode return loss 50MHz to 5GHz at 90Ω –6.5 dB
CTX-AC(COUPLING) External required AC-coupling capacitor 75 265 nF
AC Characteristics
Crosstalk Differential crosstalk between TX and RX signal pairs At 5GHz; EQ = 0; –34 dB
CPLF-LINRL0 Low-frequency –1dB compression point at LINR_L0 setting.  At 100MHz, 200mVpp < VID < 1200mVpp, EQ = 0 750 mVppd
CPHF-LINRL0 High-frequency –1dB compression point at LINR_L0 setting.   At 5GHz, 200mVpp < VID < 1200mVpp, EQ = 0 675 mVppd
CPLF-LINRL1 Low-frequency –1dB compression point at LINR_L1 setting.   At 100MHz, 200mVpp < VID < 1200mVpp, EQ = 0 850 mVppd
CPHF-LINRL1 High-frequency –1dB compression point at LINR_L1 setting.   At 5GHz, 200mVpp < VID < 1200mVpp, EQ = 0 740 mVppd
CPLF-LINRL2 Low-frequency –1dB compression point at LINR_L2 setting.   At 100MHz, 200mVpp < VID < 1200mVpp, EQ = 0 975 mVppd
CPHF-LINRL2 High-frequency –1dB compression point at LINR_L2 setting.   At 5GHz, 200mVpp < VID < 1200mVpp, EQ = 0 800 mVppd
CPLF-LINRL3 Low-frequency –1dB compression point at LINR_L3 setting.   At 100MHz, 200mVpp < VID < 1200mVpp, EQ = 0 1050 mVppd
CPHF-LINRL3 High-frequency –1dB compression point at LINR_L3 setting.   At 5GHz, 200mVpp < VID < 1200mVpp, EQ = 0 775 mVppd
tTX_DJ TX output deterministic residual jitter VID = 1Vppd; Optimual EQ setting; 12in prechannel (SDD21 = –8.2dB at 5GHz); 1.6in post channel (SDD21 = –1.8dB at 5GHz); PRBS7; USB3 at 10Gbps 0.1 UI
tTX_DJ TX output deterministic residual jitter VID = 0.8Vppd; Optimual EQ setting; 12in prechannel (SDD21 = –8.2dB at 5GHz); 1.6in post channel (SDD21 = –1.8dB at 5GHz); PRBS7; DP at 10Gbps 0.1 UI
DisplayPort Receiver (DP[3:0]p/n)
VID(PP) Peak-to-peak input differential dynamic voltage range 1400 V
VIC Input common-mode voltage 0.8 1.75 2 V
VRX_CM-INST Maximum instantaneous RX DC common-mode voltage change under following operating states:  OFF to ON, Disabled to 4DP low power, 4DP active to Disabled. (1)  Measured single-ended at non-redriver side of AC-coupling capacitor with 200kΩ load. –1200 1000 mV
VRX_CM-INST Maximum instantaneous RX DC common-mode voltage change under following operating states:  Disabled to 4DP active (D0), D0 to D3, D3 to D0. Measured single-ended at non-redriver side of AC-coupling capacitor with  50Ω load. –500 1000 mV
dR Data rate 10 Gbps
R(ti) Input termination resistance 72 90 110 Ω
C(AC) External required AC-coupling capacitor 75 265 nF
EQ_DP0 DP0 Receiver equalization at 100MHz FLIPSEL = 0; DP0EQ_SEL = 0; –0.2 dB
EQ_DP15 DP0 Receiver equalization at 100MHz FLIPSEL = 0; DP0EQ_SEL = 15; 2.3 dB
EQ_DP0 DP0 Receiver equalization at 4.05GHz FLIPSEL = 0; DP0EQ_SEL = 0; 0.6 dB
EQ_DP15 DP0 Receiver equalization at 4.05GHz FLIPSEL = 0; DP0EQ_SEL = 15; 14.5 dB
EQ_DP15 DP0 Receiver equalization at 5GHz FLIPSEL = 0; DP0EQ_SEL = 15; 14.4 dB
DisplayPort Transmitter (TX1p/n, TX2p/n, RX1p/n, RX2p/n)
VTX-CM-INST Maximum instantaneous TX DC common-mode voltage change for following operating states: Disabled to 4DP active (D0), D0 to D3, D3 to D0. Measured at non-redriver side of AC-coupling capacitor with 50Ω load. –500 1000 mV
VTX-CM-INST Maximum instantaneous TX DC common-mode voltage change under following operating states: Disabled to 4DP low power, 4DP active to Disabled Measured at non-redriver side of AC-coupling capacitor with 200kΩ load. –1000 1000 mV
VTX(DC-CM) Common-mode voltage bias in the transmitter (DC) 0.6 1 V
RTX(DIFF) Differential impedance of the driver 72 90 120 Ω
AUXp or AUXn and SBU1 or SBU2
RON Output ON resistance VCC = 3.3V; VI = 0V to 0.4V for AUXp;
VI = 2.7V to 3.6V for AUXn		 6 Ω
ΔRON ON resistance mismatch within pair VCC = 3.3V; VI = 0V to 0.4V for AUXP;
VI = 2.7V to 3.6V for AUXN		 1.0 Ω
RON(FLAT) ON resistance flatness (RON max – RON min) measured at identical VCC and temperature VCC = 3.3V; VI = 0V to 0.4V for AUXp;
VI = 2.7V to 3.6V for AUXn		 1.0 Ω
V(AUXP_DC_CM) AUX Channel DC common-mode voltage for AUXp and SBU1. VCC = 3.3V; 0 0.4 V
V(AUXN_DC_CM) AUX Channel DC common-mode voltage for AUXn and SBU2 VCC = 3.3V; 2.7 3.6 V
(1) Instantaneous common-mode excursions observed by GPU (DPTX) can be minimized by disabling redriver prior to disabling DPTX termination.