SLLSFZ7 February   2025 TUSB1146-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.2
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration In I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Linear EQ Configuration
      5. 6.4.5 Linearity VOD
      6. 6.4.6 VOD Modes
        1. 6.4.6.1 Linearity VOD
        2. 6.4.6.2 Limited VOD
      7. 6.4.7 Transmit Equalization
      8. 6.4.8 USB3.2 Modes
      9. 6.4.9 Downstream Facing Port Adaptive Equalization
        1. 6.4.9.1 Fast Adaptive Equalization in I2C Mode
        2. 6.4.9.2 Full Adaptive Equalization
        3. 6.4.9.3 Full Adaptive Equalization in GPIO Mode (I2C_EN = "F")
    5. 6.5 Programming
      1. 6.5.1 Transition Between Modes
      2. 6.5.2 Pseudocode Examples
        1. 6.5.2.1 Fast AEQ With Linear Redriver Mode
        2. 6.5.2.2 Fast AEQ With Limited Redriver Mode
        3. 6.5.2.3 Full AEQ With Linear Redriver Mode
        4. 6.5.2.4 Full AEQ With Limited Redriver Mode
      3. 6.5.3 TUSB1146-Q1 I2C Address Options
      4. 6.5.4 TUSB1146-Q1 I2C Target Behavior
  9. 7 Register Maps
    1. 7.1 TUSB1146-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C Receptacle) Configuration
        2. 8.2.2.2 USB Downstream Facing Port (USB-C Receptacle to USB Host) Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Fast Adaptive Equalization
          3. 8.2.2.2.3 Full Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2-Lane DisplayPort Mode
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.1 Device Configuration in GPIO Mode

The TUSB1146-Q1 is in GPIO configuration when I2C_EN = “0” or when I2C_EN = "F" and !(EQ0 = "0" and EQ1 = "0"). The TUSB1146-Q1 supports the following configurations: USB 3.2 only, 2 DisplayPort lanes + USB 3.2, or 4 DisplayPort lanes (no USB 3.2). The CTL1 pin controls whether DisplayPort is enabled. The combination of CTL1 and CTL0 selects between USB 3.2 only, 2 lanes of DisplayPort, or 4 lanes of DisplayPort as detailed in Table 6-2. The AUXp or AUXn to SBU1 or SBU2 mapping is controlled based on Table 6-3.

After power-up (VCC from 0V to 3.3V), the TUSB1146-Q1 defaults to USB3.2 mode. The USB PD controller upon detecting no device attached to Type-C port or USB3.2 operation not required by attached device must take TUSB1146-Q1 out of USB3.2 mode by transitioning the CTL0 pin from L to H and back to L.

Table 6-2 GPIO Configuration Control
CTL1 PIN CTL0 PIN FLIP PIN TUSB1146-Q1 CONFIGURATION VESA DisplayPort ALT MODE
DFP_D CONFIGURATION
L L L Power Down —
L L H Power Down —
L H L One Port USB 3.2 – No Flip —
L H H One Port USB 3.2 – With Flip —
H L L 4 Lane DP – No Flip C and E
H L H 4 Lane DP – With Flip C and E
H H L One Port USB 3.2 + 2 Lane DP – No Flip D
H H H One Port USB 3.2 + 2 Lane DP – With Flip D
Table 6-3 GPIO AUXp or AUXn to SBU1 or SBU2 Mapping
CTL1 PIN FLIP PIN MAPPING
H L AUXp → SBU1
AUXn → SBU2
H H AUXp → SBU2
AUXn → SBU1
L > 2ms X Open

Table 6-4 shows the mux routing of the TUSB1146-Q1 device. This table is valid for both I2C and GPIO configuration modes.

Table 6-4 INPUT to OUTPUT Mapping
CTL1 PIN CTL0 PIN FLIP PIN FROM TO
INPUT PIN OUTPUT PIN
L L L NA NA
L L H NA NA
L H L RX1P SSRXP
RX1N SSRXN
SSTXP TX1P
SSTXN TX1N
L H H RX2P SSRXP
RX2N SSRXN
SSTXP TX2P
SSTXN TX2P
H L L DP0P RX2P
DP0N RX2N
DP1P TX2P
DP1N TX2N
DP2P TX1P
DP2N TX1N
DP3P RX1P
DP3N RX1N
H L H DP0P RX1P
DP0N RX1N
DP1P TX1P
DP1N TX1N
DP2P TX2P
DP2N TX2N
DP3P RX2P
DP3N RX2N
H H L RX1P SSRXP
RX1N SSRXN
SSTXP TX1P
SSTXN TX1N
DP0P RX2P
DP0N RX2N
DP1P TX2P
DP1N TX2N
H H H RX2P SSRXP
RX2N SSRXN
SSTXP TX2P
SSTXN TX2N
DP0P RX1P
DP0N RX1N
DP1P TX1P
DP1N TX1N