SLLSFZ7 February   2025 TUSB1146-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.2
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration In I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Linear EQ Configuration
      5. 6.4.5 Linearity VOD
      6. 6.4.6 VOD Modes
        1. 6.4.6.1 Linearity VOD
        2. 6.4.6.2 Limited VOD
      7. 6.4.7 Transmit Equalization
      8. 6.4.8 USB3.2 Modes
      9. 6.4.9 Downstream Facing Port Adaptive Equalization
        1. 6.4.9.1 Fast Adaptive Equalization in I2C Mode
        2. 6.4.9.2 Full Adaptive Equalization
        3. 6.4.9.3 Full Adaptive Equalization in GPIO Mode (I2C_EN = "F")
    5. 6.5 Programming
      1. 6.5.1 Transition Between Modes
      2. 6.5.2 Pseudocode Examples
        1. 6.5.2.1 Fast AEQ With Linear Redriver Mode
        2. 6.5.2.2 Fast AEQ With Limited Redriver Mode
        3. 6.5.2.3 Full AEQ With Linear Redriver Mode
        4. 6.5.2.4 Full AEQ With Limited Redriver Mode
      3. 6.5.3 TUSB1146-Q1 I2C Address Options
      4. 6.5.4 TUSB1146-Q1 I2C Target Behavior
  9. 7 Register Maps
    1. 7.1 TUSB1146-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C Receptacle) Configuration
        2. 8.2.2.2 USB Downstream Facing Port (USB-C Receptacle to USB Host) Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Fast Adaptive Equalization
          3. 8.2.2.2.3 Full Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2-Lane DisplayPort Mode
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2 DisplayPort

The TUSB1146-Q1 supports up to four DisplayPort lanes at datarates up to 10Gbps. The TUSB1146-Q1, when configured in DisplayPort mode, monitors the native AUX traffic as the flow traverses between DisplayPort source and DisplayPort sink. For the purposes of reducing power, the TUSB1146-Q1 manages the number of active DisplayPort lanes based on the content of the AUX transactions. The TUSB1146-Q1 snoops native AUX writes to the DPCD registers 0x00101 (LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE) of the DisplayPort sink. The TUSB1146-Q1 disables or enables lanes based on value written to LANE_COUNT_SET. The TUSB1146-Q1 disables all lanes when SET_POWER_STATE is in the D3. Otherwise active lanes are based on value of LANE_COUNT_SET.

DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE register. When AUX snoop is disabled, management of TUSB1146-Q1 DisplayPort lanes are controlled through various configuration registers. When TUSB1146-Q1 is enabled for GPIO mode (I2C_EN = "0"), the CAD_SNK pin can be used to disable AUX snooping. When CAD_SNK pin is high, the AUX snooping functionality is disabled and all four DisplayPort lanes are active.