SLLSFZ7 February   2025 TUSB1146-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Supply Characteristics
    6. 5.6  Control I/O DC Electrical Characteristics
    7. 5.7  USB and DP Electrical Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 USB 3.2
      2. 6.3.2 DisplayPort
      3. 6.3.3 4-Level Inputs
      4. 6.3.4 Receiver Linear Equalization
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Configuration in GPIO Mode
      2. 6.4.2 Device Configuration In I2C Mode
      3. 6.4.3 DisplayPort Mode
      4. 6.4.4 Linear EQ Configuration
      5. 6.4.5 Linearity VOD
      6. 6.4.6 VOD Modes
        1. 6.4.6.1 Linearity VOD
        2. 6.4.6.2 Limited VOD
      7. 6.4.7 Transmit Equalization
      8. 6.4.8 USB3.2 Modes
      9. 6.4.9 Downstream Facing Port Adaptive Equalization
        1. 6.4.9.1 Fast Adaptive Equalization in I2C Mode
        2. 6.4.9.2 Full Adaptive Equalization
        3. 6.4.9.3 Full Adaptive Equalization in GPIO Mode (I2C_EN = "F")
    5. 6.5 Programming
      1. 6.5.1 Transition Between Modes
      2. 6.5.2 Pseudocode Examples
        1. 6.5.2.1 Fast AEQ With Linear Redriver Mode
        2. 6.5.2.2 Fast AEQ With Limited Redriver Mode
        3. 6.5.2.3 Full AEQ With Linear Redriver Mode
        4. 6.5.2.4 Full AEQ With Limited Redriver Mode
      3. 6.5.3 TUSB1146-Q1 I2C Address Options
      4. 6.5.4 TUSB1146-Q1 I2C Target Behavior
  9. 7 Register Maps
    1. 7.1 TUSB1146-Q1 Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 USB and DP Upstream Facing Port (USB Host / DP GPU to USB-C Receptacle) Configuration
        2. 8.2.2.2 USB Downstream Facing Port (USB-C Receptacle to USB Host) Configuration
          1. 8.2.2.2.1 Fixed Equalization
          2. 8.2.2.2.2 Fast Adaptive Equalization
          3. 8.2.2.2.3 Full Adaptive Equalization
        3. 8.2.2.3 ESD Protection
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 USB 3.1 Only
      2. 8.3.2 USB 3.1 and 2-Lane DisplayPort Mode
      3. 8.3.3 DisplayPort Only
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TUSB1146-Q1 TUSB1146-Q1 RGF Package, 40-Pin VQFN (Top View) Figure 4-1 TUSB1146-Q1 RGF Package, 40-Pin VQFN (Top View)
Table 4-1 TUSB1146-Q1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
DP0p 1 Diff I DP Differential positive input for DisplayPort Lane 0.
DP0n 2 Diff I DP Differential negative input for DisplayPort Lane 0.
DP1p 4 Diff I DP Differential positive input for DisplayPort Lane 1.
DP1n 5 Diff I DP Differential negative input for DisplayPort Lane 1.
DP2p 7 Diff I DP Differential positive input for DisplayPort Lane 2.
DP2n 8 Diff I DP Differential negative input for DisplayPort Lane 2.
DP3p 10 Diff I DP Differential positive input for DisplayPort Lane 3.
DP3n 11 Diff I DP Differential negative input for DisplayPort Lane 3.
RX1n 23 Diff I/O Differential negative output for DisplayPort or differential negative input for USB3.2 Downstream Facing port.
RX1p 22 Diff I/O Differential positive output for DisplayPort or differential positive input for USB3.2 Downstream Facing port.
TX1n 26 Diff O Differential negative output for DisplayPort or USB3.2 downstream facing port.
TX1p 25 Diff O Differential positive output for DisplayPort or USB 3.2 downstream facing port.
TX2p 29 Diff O Differential positive output for DisplayPort or USB 3.2 downstream facing port.
TX2n 28 Diff O Differential negative output for DisplayPort or USB 3.2 downstream facing port.
RX2p 32 Diff I/O Differential positive output for DisplayPort or differential positive input for USB3.2 Downstream Facing port.
RX2n 31 Diff I/O Differential negative output for DisplayPort or differential negative input for USB3.2 Downstream Facing port.
SSTXp 40 Diff I Differential positive input for USB3.2 upstream facing port.
SSTXn 39 Diff I Differential negative input for USB3.2 upstream facing port.
SSRXp 37 Diff O Differential positive output for USB3.2 upstream facing port.
SSRXn 36 Diff O Differential negative output for USB3.2 upstream facing port.
EQ1 27 4 Level I This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. Refer to Table 6-7 for details on the equalization setting.
EQ0 30 4 Level I This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. Refer to Table 6-7 for details on the equalization setting.
CAD_SNK/RSVD1(1) 21 I/O
(PD)		 When I2C_EN ! = 0, this pin is reserved. Leave open if not used. When I2C_EN = 0 , this pin is CAD_SNK (L = AUX snoop enabled and H = AUX snoop disabled with all lanes active).
HPDIN/RSVD2(1) 24 I/O
(PD)		 When I2C_EN ! = 0, this pin is reserved. Leave open if not used. When I2C_EN = 0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled while the AUX-to-SBU switch remains closed.
I2C_EN 9 4 Level I I2C Programming Mode or GPIO Programming Select.
0 = GPIO mode (I2C disabled) with adaptive EQ disabled.
R = TI Test Mode (I2C enabled at 3.3V)
F = I2C enabled at 1.8V when EQ0 = "0" and EQ1 = "0". Otherwise, GPIO mode (I2C disabled) with adaptive EQ enabled.
1 = I2C enabled at 3.3V.
SBU1 19 I/O, CMOS SBU1. TI recommends to DC-couple this pin to the SBU1 pin on the Type-C receptacle. A 2MΩ resistor to GND is also recommended.
SBU2 18 I/O, CMOS SBU2. TI recommends to DC-couple this pin to the SBU2 pin on the Type-C receptacle. A 2MΩ resistor to GND is also recommended.
AUXp 16 I/O, CMOS AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source through a AC-coupling capacitor. In addition to AC-coupling capacitor, this pin also requires a 100K resistor to GND. This pin along with AUXN is used by the TUSB1146-Q1 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C.
AUXn 17 I/O, CMOS AUXn. DisplayPort AUX negative I/O connected to the DisplayPort source through a AC-coupling capacitor. In addition to AC- coupling capacitor, this pin also requires a 100K resistor to VCC (3.3V). This pin along with AUXP is used by the TUSB1146-Q1 for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C.
DPEQ1 34 4 Level I DisplayPort Receiver EQ. Along with DPEQ0, this pin selects the DisplayPort receiver equalization gain. Refer to Table 6-9 for details on the equalization settings.
DPEQ0/A1 6 4 Level I DisplayPort Receiver EQ. Along with DPEQ1, this pin selects the DisplayPort receiver equalization gain. When I2C_EN is not ‘0’, this pin also sets the TUSB1146-Q1 I2C address. Refer to Table 6-9 for details on the equalization settings.
SSEQ1 35 4 Level I Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N. Refer to Table 6-8 for details on the equalization settings.
SSEQ0/A0 3 4 Level I Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When I2C_EN is not ‘0’, this pin also sets the TUSB1146-Q1 I2C address. Refer to Table 6-8 for details on the equalization settings.
FLIP/SCL 13 2 Level I When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. When used for I2C clock, pull up the pin to the VCC I2C supply of the I2C controller.
CTL0/SDA 14 2 Level I When I2C_EN=’0’ this is a USB3 Switch control pin, otherwise this pin is I2C data. When used for I2C data, pull up the pin to the VCC I2C supply of the I2C controller.
CTL1/HPDIN 15 2 Level I
(Failsafe)
(PD)		 DP Alt mode Switch Control Pin. When I2C_EN = ‘0’, this pin enables or disables DisplayPort functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled.
H = DisplayPort Enabled.
When I2C_EN is not "0" this pin is an input for Hot Plug Detect received from DisplayPort sink. When this HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled and AUX-to-SBU switch remains closed.
VCC 12, 20, 33, 38 P 3.3V Power Supply
Thermal Pad G Ground
(1) Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.