3.3 Hardware Troubleshooting Guidelines

Normally, hardware troubleshooting take more time than the software method because the EUT enclosure, mechanical, cable connection, or board layout may need to be changed. It is better to have an efficient software simulation tools to do the system-level ESD simulation and then use Signal Integrity/Power Integrity (SI/PI) simulation to address the board weak points before the board fabrication. Then the potential EMC issue can be avoided in the design phase.

The ESD simulation tool is also very helpful when debugging the ESD test failures. But the ESD simulation is not very easy to implement because accurate modeling setup is relatively difficult and the simulation tools are normally expensive. So in most cases, hardware troubleshooting and workaround are required.

Generally, the system-level ESD issue troubleshooting is conducted from two respects.

• Path control for noise transmission

Guide the noise to transmit to GND quickly without passing the critical sensitive components.

• Improve the noise filter performance

Try to filter the noise in noise transmission path.

It is recommended to start the system review from these two aspects. The following are hardware debug examples recommended for trial.

1. Review the enclosure mechanical construction around the PCB. Try to reduce the ESD leakage possibility. Check if there is good grounding for the metal on the enclosure. If there is floating metal on the enclosure close to the PCB, try to move the PCB or sensitive components far away from the metal. Cable entry is another important point to review. See MSP430 System-Level ESD Considerations for design guidelines including enclosure grounding, openings, and cable entry.
2. Review the PCB layout. Check the ESD noise transmission path from the discharge point. Place critical components far away from the path. Try to reduce the transmission path resistance, or change the path by board layout rework. Adding isolation is also a path control option. Signal return path is very important, especially for the sensitive signals. See MSP430 System-Level ESD Considerations for more PCB design guidelines.
3. If the root cause of the failure is as related to the crystal clock, try to increase the crystal circuit robustness by checking the load capacitance match, crystal circuit layout and drive strength setting. See MSP430 32-kHz Crystal Oscillators and MSP430 System-Level ESD Considerations for more details about the crystal circuit design.
4. Use recommended reset circuit for better reset pin protection

The reset pin and test pin signals are important for SBW communication. Keep these two signal traces as short as possible in board layout. In addition, from the MSP430 data sheets and the MSP430 Hardware Tools User's Guide, the parallel capacitor on the reset trace should be less than 2.2 nF or 1.1 nF. When a large noise occurs on the reset pin, the capacitor may not be enough to filter. To improve this, the circuit in Figure 2 is recommended to increase the filter capability for the noise on the reset pin.

Figure 2. Recommended SBW Circuit for MSP430 MCUs

In the Figure 2, a 10-µF or larger capacitor can be used for C8. Resistor R12 works as isolation for the capacitors C8 and C9. With this circuit, JTAG and SBW can work well and the noise filter capability of the reset signal path is also improved.

5. Add a pulldown resistor on the TEST pin

The TEST pin has built-in pulldown resistor to confirm it is in low logic during firmware execution. Normally, the built-in pulldown resistor is weak. Add an external smaller pulldown resistor to see if the ESD failure is related to a TEST pin logic error.

6. Add a series resistor and parallel capacitor in long signal traces to reduce the EMI impact

The values of the series resistor and parallel capacitor to add depend on the signal speed and drive strength. Normally, the value should not be big so that the signals are not impacted too much. If the ESD failure is related to the LCD, this method can be tried.

7. Increase the decoupling capacitor value or add TVS for power traces

If the power trace is a weak point for the ESD test from the reset source check introduced in Section 3.2, increase the decoupling capacitor value for trial. A capacitor bigger than 22 µF can be tested. Power TVS can also be added for the test.

If there are multiple boards in the system and the power is transmitted on an internal cable, add a decoupling capacitor on the power pin at the receiving connector side.

8. Add TVS on signal traces connected to an external interface

For signals connected to external interface, it is important to have ESD protection. A signal TVS can be used for this purpose. Serial resistors can also be an option. In addition to TVS, more ESD suppression devices can be used. See MSP430 System-Level ESD Considerations for more details.

9. Add shielding to isolate EMI impact over the air

If the EMI noise from the air interferes with the EUT, add GND shielding between the EMI source and the EUT to isolate them.

10. Add GND shielding on cables connected between boards especially for flat cables.
11. Use the latest revision MCU material

Usually newer version silicon have more reliable system-level ESD performance.

12. Use failure analysis process

Some system-level ESD failures are hard to reproduce. Normally, a power cycle will recover the system and it is hard to reproduce it in short term. The MCU may have abnormal electrical behavior such as higher power consumption and big voltage drop. For this case, it is mostly like a latch-up issue occurs at some pins or modules of the silicon, and a failure analysis procedure for troubleshooting is discussed in Section 4.

Sometimes, several workarounds can work together to fix the issue.