SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
Buffering of clock and signals are recommended whenever the JTAG interface connects to more than one device. Buffering of clock is recommended even for single device implementations. For implementation, see the device-specific SK.
If trace operation is used, connect TRC_x signals directly to the emulation connector. All TRC_x signals are pin-muxed with other signals. Either trace functionality or GPMC interface can be used. Connections (Board trace) for TRC_x signals used for trace functionality must be short and skew matched. The trace signals are on VDDSHV3 Dual-voltage IO domain, and can be at a different supply voltage from the other JTAG signals. For additional recommendations on TRC/EMU design and layout, see the Emulation and Trace Headers Technical Reference Manual. A summary of this information is available in the XDS Target Connection Guide.
If boundary scan is used, connect EMU0 and EMU1 pins directly to the JTAG connector.
For proper implementation of the JTAG interface, see the Emulation and Trace Headers Technical Reference Manual and the XDS Target Connection Guide.