SPRAD21E May 2023 – February 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
Provide provision for adding parallel pulls to the processor IOs. Parallel pull polarity and the values are dependent on the specific peripheral connectivity recommendations, recommendations for improved processor performance and relevant interface or standards requirements.
Device-specific SK pull values can be used as a starting point and board designers can choose the appropriate pull values based on the recommendations for the processor and attached device or specific board design implementation.
When a trace is connected to the processor pads and not being actively driven, a parallel pull is recommended (pull polarity is customer use case dependent). During power-up, processor IO buffers are off and the IOs are in high impedance state (effectively an antenna that will pick up noise). Without any termination, these signal are very high impedance. This makes it easy for noise to couple energy on these floating signal trace and develop a potential that could exceed our recommended operating conditions, which would create an Electrical Over-Stress (EOS) on the IOs. ESD protection circuits inside the processor were only designed to protect the device from handling before being installed on a PCB assembly.