SPRUJ79 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 â–º C29x SYSTEM RESOURCES
    1.     Technical Reference Manual Overview
  4. 2 F29x Processor
    1. 2.1 CPU Architecture
      1. 2.1.1 C29x Related Collateral
    2. 2.2 Lock and Commit Registers
    3. 2.3 C29x CPU Registers
      1. 2.3.1 C29CPU Base Address Table
      2. 2.3.2 C29_RTINT_STACK Registers
      3. 2.3.3 C29_SECCALL_STACK Registers
      4. 2.3.4 C29_SECURE_REGS Registers
      5. 2.3.5 C29_DIAG_REGS Registers
      6. 2.3.6 C29_SELFTEST_REGS Registers
  5. 3 System Control and Interrupts
    1. 3.1  C29x System Control Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1 Reset Sources
      2. 3.3.2 External Reset (XRS)
      3. 3.3.3 Simulate External Reset
      4. 3.3.4 Power-On Reset (POR)
      5. 3.3.5 Debugger Reset (SYSRS)
      6. 3.3.6 Watchdog Reset (WDRS)
      7. 3.3.7 ESM NMI Watchdog Reset (NMIWDRS)
      8. 3.3.8 EtherCAT Slave Controller (ESC) Module Reset Output
    4. 3.4  Safety Features
      1. 3.4.1 Write Protection on Registers
        1. 3.4.1.1 LOCK Protection on System Configuration Registers
        2. 3.4.1.2 EALLOW Protection
      2. 3.4.2 PIPE Vector Address Validity Check
      3. 3.4.3 NMIWDs
      4. 3.4.4 System Control Registers Parity Protection
      5. 3.4.5 ECC Enabled RAMs, Shared RAMs Protection
      6. 3.4.6 ECC Enabled Flash Memory
      7. 3.4.7 ERRORSTS Pin
    5. 3.5  Clocking
      1. 3.5.1 Clock Sources
        1. 3.5.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.5.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.5.1.3 External Oscillator (XTAL)
        4. 3.5.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.5.2 Derived Clocks
        1. 3.5.2.1 Oscillator Clock (OSCCLK)
        2. 3.5.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.5.3 Device Clock Domains
        1. 3.5.3.1 System Clock (PLLSYSCLK)
        2. 3.5.3.2 CPU Clock (CPUCLK)
        3. 3.5.3.3 Peripheral Clock (PERx.SYSCLK)
        4. 3.5.3.4 MCAN Bit Clock
        5. 3.5.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.5.4 External Clock Output (XCLKOUT)
      5. 3.5.5 Clock Connectivity
      6. 3.5.6 Using an External Crystal or Resonator
        1. 3.5.6.1 X1/X2 Precondition Circuit
      7. 3.5.7 PLL
        1. 3.5.7.1 System Clock Setup
        2. 3.5.7.2 SYS PLL Bypass
      8. 3.5.8 Clock (OSCCLK) Failure Detection
        1. 3.5.8.1 Missing Clock Detection Logic
        2. 3.5.8.2 Dual Clock Comparator (DCC)
    6. 3.6  Bus Architecture
      1. 3.6.1 Safe Interconnect
        1. 3.6.1.1 Safe Interconnect for Read Operation
        2. 3.6.1.2 Safe Interconnect for Write Operation
      2. 3.6.2 Peripheral Access Configuration using FRAMESEL
      3. 3.6.3 Bus Arbitration
    7. 3.7  32-Bit CPU Timers 0/1/2
    8. 3.8  Watchdog Timers
      1. 3.8.1 Servicing the Watchdog Timer
      2. 3.8.2 Minimum Window Check
      3. 3.8.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.8.4 Watchdog Operation in Low-Power Modes
      5. 3.8.5 Emulation Considerations
    9. 3.9  Low-Power Modes
      1. 3.9.1 IDLE
      2. 3.9.2 STANDBY
    10. 3.10 Memory Subsystem (MEMSS)
      1. 3.10.1 Introduction
      2. 3.10.2 Features
      3. 3.10.3 Configuration Bits
        1. 3.10.3.1 Memory Initialization
      4. 3.10.4 RAM
        1. 3.10.4.1  MEMSS Architecture
        2. 3.10.4.2  RAM Memory Controller Overview
        3. 3.10.4.3  Memory Controllers
          1. 3.10.4.3.1 128-Bit LPx and CPx Memory Controller
          2. 3.10.4.3.2 64-Bit LDx and CDx Memory Controller
          3. 3.10.4.3.3 M0 Memory Controller
        4. 3.10.4.4  RTDMA Burst Support
        5. 3.10.4.5  Atomic Memory Operations
        6. 3.10.4.6  RAM ECC
        7. 3.10.4.7  Read-Modify-Write Operations
        8. 3.10.4.8  Dataline Buffer
        9. 3.10.4.9  HSM Sync Bridge
        10. 3.10.4.10 Access Bridges
          1. 3.10.4.10.1 Debug Access Bridge
          2. 3.10.4.10.2 Global Access Bridge
          3. 3.10.4.10.3 Program Access Bridge
      5. 3.10.5 ROM
        1. 3.10.5.1 ROM Dataline Buffer
        2. 3.10.5.2 ROM Prefetch
      6. 3.10.6 Arbitration
      7. 3.10.7 Test Modes
      8. 3.10.8 Emulation Mode
    11. 3.11 System Control Register Configuration Restrictions
    12. 3.12 Software
      1. 3.12.1  SYSCTL Registers to Driverlib Functions
      2. 3.12.2  MEMSS Registers to Driverlib Functions
      3. 3.12.3  CPU Registers to Driverlib Functions
      4. 3.12.4  WD Registers to Driverlib Functions
      5. 3.12.5  CPUTIMER Registers to Driverlib Functions
      6. 3.12.6  XINT Registers to Driverlib Functions
      7. 3.12.7  LPOST Registers to Driverlib Functions
      8. 3.12.8  SYSCTL Examples
        1. 3.12.8.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 3.12.8.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      9. 3.12.9  TIMER Examples
        1. 3.12.9.1 Timer Academy Lab - SINGLE_CORE
        2. 3.12.9.2 CPU Timers - SINGLE_CORE
        3. 3.12.9.3 CPU Timers - SINGLE_CORE
      10. 3.12.10 WATCHDOG Examples
        1. 3.12.10.1 Watchdog - SINGLE_CORE
      11. 3.12.11 LPM Examples
        1. 3.12.11.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO - SINGLE_CORE
        2. 3.12.11.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog - SINGLE_CORE
        3. 3.12.11.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO - SINGLE_CORE
        4. 3.12.11.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog - SINGLE_CORE
    13. 3.13 SYSCTRL Registers
      1. 3.13.1  SYSCTRL Base Address Table
      2. 3.13.2  DEV_CFG_REGS Registers
      3. 3.13.3  MEMSS_L_CONFIG_REGS Registers
      4. 3.13.4  MEMSS_C_CONFIG_REGS Registers
      5. 3.13.5  MEMSS_M_CONFIG_REGS Registers
      6. 3.13.6  MEMSS_MISCI_REGS Registers
      7. 3.13.7  CPU_SYS_REGS Registers
      8. 3.13.8  CPU_PER_CFG_REGS Registers
      9. 3.13.9  WD_REGS Registers
      10. 3.13.10 CPUTIMER_REGS Registers
      11. 3.13.11 XINT_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Device Boot Flow
      2. 4.5.2 CPU1 Boot Flow
      3. 4.5.3 Emulation Boot Flow
      4. 4.5.4 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 MPOST and LPOST Configurations
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Memory Maps
        1. 4.7.4.1 Boot ROM Memory-Maps
        2. 4.7.4.2 Reserved RAM Memory-Maps
      5. 4.7.5  ROM Structure and Status Information
      6. 4.7.6  Boot Modes and Loaders
        1. 4.7.6.1 Boot Modes
          1. 4.7.6.1.1 Flash Boot
          2. 4.7.6.1.2 RAM Boot
          3. 4.7.6.1.3 Wait Boot
        2. 4.7.6.2 Bootloaders
          1. 4.7.6.2.1 SPI Boot Mode
          2. 4.7.6.2.2 I2C Boot Mode
          3. 4.7.6.2.3 Parallel Boot Mode
          4. 4.7.6.2.4 CAN Boot Mode
          5. 4.7.6.2.5 CAN-FD Boot Mode
          6. 4.7.6.2.6 UART Boot Mode
      7. 4.7.7  GPIO Assignments
      8. 4.7.8  HSM and C29 ROM Task Ownership and Interactions
        1. 4.7.8.1 Application Authentication by HSM
      9. 4.7.9  Boot Status Information
        1. 4.7.9.1 Booting Status
      10. 4.7.10 BootROM Timing
    8. 4.8 Software
      1. 4.8.1 BOOT Examples
  7. 5 Lockstep Compare Module (LCM)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
      3. 5.1.3 Lockstep Compare Modules
    2. 5.2 Enabling LCM Comparators
    3. 5.3 LCM Redundant Module Configuration
    4. 5.4 LCM Error Handling
    5. 5.5 Debug Mode with LCM
    6. 5.6 Register Parity Error Protection
    7. 5.7 Functional Logic
      1. 5.7.1 Comparator Logic
      2. 5.7.2 Self-Test Logic
        1. 5.7.2.1 Match Test Mode
        2. 5.7.2.2 Mismatch Test Mode
      3. 5.7.3 Error Injection Tests
        1. 5.7.3.1 Comparator Error Force Test
        2. 5.7.3.2 Register Parity Error Test
    8. 5.8 Software
      1. 5.8.1 LCM Registers to Driverlib Functions
    9. 5.9 LCM Registers
      1. 5.9.1 LCM Base Address Table
      2. 5.9.2 LCM_REGS Registers
  8. 6 Peripheral Interrupt Priority and Expansion (PIPE)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 Interrupt Concepts
      3. 6.1.3 PIPE Related Collateral
    2. 6.2 Interrupt Architecture
      1. 6.2.1 Dynamic Priority Arbitration Block
      2. 6.2.2 Post Processing Block
      3. 6.2.3 Memory-Mapped Registers
    3. 6.3 Interrupt Propagation
    4. 6.4 Configuring Interrupts
      1. 6.4.1 Enabling and Disabling Interrupts
      2. 6.4.2 Prioritization
        1. 6.4.2.1 User-Configured Interrupt Priority
        2. 6.4.2.2 Index-Based Fixed Interrupt Priority
      3. 6.4.3 Nesting and Priority Grouping
      4. 6.4.4 Stack Protection
      5. 6.4.5 Context
    5. 6.5 Safety and Security
      1. 6.5.1 Access Control
      2. 6.5.2 PIPE Errors
      3. 6.5.3 Register Data Integrity and Safety
      4. 6.5.4 Self-Test and Diagnostics
    6. 6.6 Software
      1. 6.6.1 PIPE Registers to Driverlib Functions
      2. 6.6.2 INTERRUPT Examples
        1. 6.6.2.1 RTINT vs INT Latency example - SINGLE_CORE
        2. 6.6.2.2 INT and RTINT Nesting Example - SINGLE_CORE
    7. 6.7 PIPE Registers
      1. 6.7.1 PIPE Base Address Table
      2. 6.7.2 PIPE_REGS Registers
  9. 7  Error Signaling Module (ESM_C29)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 ESM Related Collateral
    2. 7.2 ESM Subsystem
      1. 7.2.1 System ESM
        1. 7.2.1.1 Error Pin Monitor Event
      2. 7.2.2 Safety Aggregator
        1. 7.2.2.1 EDC Controller Interface Description
          1. 7.2.2.1.1 EDC_REGS Registers
        2. 7.2.2.2 Read Operation on EDC Controller
        3. 7.2.2.3 Write Operation on EDC Controller
        4. 7.2.2.4 Safety Aggregator Error Injection
      3. 7.2.3 ESM Subsystem Integration View
    3. 7.3 ESM Functional Description
      1. 7.3.1 Error Event Inputs
      2. 7.3.2 Error Interrupt Outputs
        1. 7.3.2.1 High Priority Watchdog
        2. 7.3.2.2 Critical Priority Interrupt Output
      3. 7.3.3 Error Pin Output (ERR_O/ERRORSTS)
        1. 7.3.3.1 Minimum Time Interval
        2. 7.3.3.2 PWM Mode
      4. 7.3.4 Reset Type Information for ESM Registers
      5. 7.3.5 Clock Stop
      6. 7.3.6 Commit/Lock for MMRs
      7. 7.3.7 Safety Protection for MMRs
      8. 7.3.8 Register Configuration Tieoffs
        1. 7.3.8.1 Group0 High Priority Tieoff
        2. 7.3.8.2 High Priority Watchdog Enable Tieoff
    4. 7.4 ESM Configuration Guide
    5. 7.5 Interrupt Condition Control and Handling
      1. 7.5.1 ESM Low Priority Error Interrupt
      2. 7.5.2 ESM High Priority Error Interrupt
      3. 7.5.3 Critical Priority Error Interrupt
      4. 7.5.4 High Priority Watchdog Interrupt
      5. 7.5.5 Safety Aggregator Interrupt Control and Handling
    6. 7.6 Software
      1. 7.6.1 ESM_CPU Registers to Driverlib Functions
      2. 7.6.2 ESM_SYS Registers to Driverlib Functions
      3. 7.6.3 ESM_SAFETY_AGGREGATOR Registers to Driverlib Functions
      4. 7.6.4 ESM Examples
        1. 7.6.4.1 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        2. 7.6.4.2 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        3. 7.6.4.3 ESM - SINGLE_CORE
        4. 7.6.4.4 ESM - SINGLE_CORE
    7. 7.7 ESM Registers
      1. 7.7.1 ESM Base Address Table
      2. 7.7.2 ESM_CPU_REGS Registers
      3. 7.7.3 ESM_SYSTEM_REGS Registers
      4. 7.7.4 ESM_SAFETYAGG_REGS Registers
  10. 8  Error Aggregator
    1. 8.1 Introduction
    2. 8.2 Error Aggregator Modules
    3. 8.3 Error Propagation Path from Source to CPU
    4. 8.4 Error Aggregator Interface
      1. 8.4.1 Functional Description
    5. 8.5 Error Condition Handling User Guide
    6. 8.6 Error Type Information
    7. 8.7 Error Sources Information
    8. 8.8 Software
      1. 8.8.1 ERROR_AGGREGATOR Registers to Driverlib Functions
    9. 8.9 ERRORAGGREGATOR Registers
      1. 8.9.1 ERRORAGGREGATOR Base Address Table
      2. 8.9.2 HSM_ERROR_AGGREGATOR_CONFIG_REGS Registers
      3. 8.9.3 ERROR_AGGREGATOR_CONFIG_REGS Registers
  11. 9 Flash Module
    1. 9.1 Introduction to Flash Memory
      1. 9.1.1 FLASH Related Collateral
      2. 9.1.2 Features
      3. 9.1.3 Flash Tools
      4. 9.1.4 Block Diagram
    2. 9.2 Flash Subsystem Overview
    3. 9.3 Flash Banks and Pumps
    4. 9.4 Flash Read Interfaces
      1. 9.4.1 Bank Modes and Swapping
      2. 9.4.2 Flash Wait States
      3. 9.4.3 Buffer and Cache Mechanisms
        1. 9.4.3.1 Prefetch Mechanism and Block Cache
        2. 9.4.3.2 Data Line Buffer
        3. 9.4.3.3 Sequential Data Pre-read Mode
      4. 9.4.4 Flash Read Arbitration
      5. 9.4.5 Error Correction Code (ECC) Protection
      6. 9.4.6 Procedure to Change Flash Read Interface Registers
    5. 9.5 Flash Erase and Program
      1. 9.5.1 Flash Semaphore and Update Protection
      2. 9.5.2 Erase
      3. 9.5.3 Program
    6. 9.6 Migrating an Application from RAM to Flash
    7. 9.7 Flash Registers
      1. 9.7.1 FLASH Base Address Table
      2. 9.7.2 FLASH_CMD_REGS_FLC1 Registers
      3. 9.7.3 FLASH_CMD_REGS_FLC2 Registers
      4. 9.7.4 FRI_CTRL_REGS Registers
  12. 10Safety and Security Unit (SSU)
    1. 10.1  Introduction
      1. 10.1.1 SSU Related Collateral
      2. 10.1.2 Block Diagram
      3. 10.1.3 System SSU Configuration Example
    2. 10.2  Access Protection Ranges
      1. 10.2.1 Access Protection Inheritance
    3. 10.3  LINKs
    4. 10.4  STACKs
    5. 10.5  ZONEs
    6. 10.6  SSU-CPU Interface
      1. 10.6.1 SSU Operation in Lockstep Mode
    7. 10.7  SSU Operation Modes
    8. 10.8  Security Configuration and Flash Management
      1. 10.8.1 BANKMGMT Sectors
      2. 10.8.2 SECCFG Sectors
      3. 10.8.3 SECCFG Sector Address Mapping
      4. 10.8.4 SECCFG Sector Memory Map
      5. 10.8.5 SECCFG CRC
    9. 10.9  Flash Write/Erase Access Control
      1. 10.9.1 Permanent Flash Lock (Write/Erase Protection)
      2. 10.9.2 Updating Flash MAIN Sectors
      3. 10.9.3 Firmware-Over-The-Air Updates (FOTA)
      4. 10.9.4 Updating Flash SECCFG Sectors
      5. 10.9.5 Reading Flash SECCFG Sectors
    10. 10.10 RAMOPEN Feature
    11. 10.11 Debug Authorization
      1. 10.11.1 Global CPU Debug Enable
      2. 10.11.2 ZONE Debug
      3. 10.11.3 Authentication for Debug Access
        1. 10.11.3.1 Password-based Authentication
        2. 10.11.3.2 CPU-based Authentication
    12. 10.12 Hardcoded Protections
    13. 10.13 SSU Register Access Permissions
      1. 10.13.1 Permissions for SSU General Control Registers
      2. 10.13.2 Permissions for SSU CPU1 Configuration Registers
      3. 10.13.3 Permissions for SSU CPU2+ Configuration Registers
      4. 10.13.4 Permissions for CPU1 Access Protection Registers
      5. 10.13.5 Permissions for CPU2+ Access Protection Registers
    14. 10.14 SSU Fault Signals
    15. 10.15 Software
      1. 10.15.1 SSU Registers to Driverlib Functions
    16. 10.16 SSU Registers
      1. 10.16.1 SSU Base Address Table
      2. 10.16.2 SSU_GEN_REGS Registers
      3. 10.16.3 SSU_CPU1_CFG_REGS Registers
      4. 10.16.4 SSU_CPU2_CFG_REGS Registers
      5. 10.16.5 SSU_CPU3_CFG_REGS Registers
      6. 10.16.6 SSU_CPU1_AP_REGS Registers
      7. 10.16.7 SSU_CPU2_AP_REGS Registers
      8. 10.16.8 SSU_CPU3_AP_REGS Registers
  13. 11Configurable Logic Block (CLB)
    1. 11.1  Introduction
      1. 11.1.1 CLB Related Collateral
    2. 11.2  Description
      1. 11.2.1 CLB Clock
    3. 11.3  CLB Input/Output Connection
      1. 11.3.1 Overview
      2. 11.3.2 CLB Input Selection
      3. 11.3.3 CLB Output Selection
      4. 11.3.4 CLB Output Signal Multiplexer
    4. 11.4  CLB Tile
      1. 11.4.1 Static Switch Block
      2. 11.4.2 Counter Block
        1. 11.4.2.1 Counter Description
        2. 11.4.2.2 Counter Operation
        3. 11.4.2.3 Serializer Mode
        4. 11.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 11.4.3 FSM Block
      4. 11.4.4 LUT4 Block
      5. 11.4.5 Output LUT Block
      6. 11.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 11.4.7 High Level Controller (HLC)
        1. 11.4.7.1 High Level Controller Events
        2. 11.4.7.2 High Level Controller Instructions
        3. 11.4.7.3 <Src> and <Dest>
        4. 11.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 11.5  CPU Interface
      1. 11.5.1 Register Description
      2. 11.5.2 Non-Memory Mapped Registers
    6. 11.6  RTDMA Access
    7. 11.7  CLB Data Export Through SPI RX Buffer
    8. 11.8  CLB Pipeline Mode
    9. 11.9  Software
      1. 11.9.1 CLB Registers to Driverlib Functions
      2. 11.9.2 CLB Examples
    10. 11.10 CLB Registers
      1. 11.10.1 CLB Base Address Table
      2. 11.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 11.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 11.10.4 CLB_DATA_EXCHANGE_REGS Registers
  14. 12Dual-Clock Comparator (DCC)
    1. 12.1 Introduction
      1. 12.1.1 Features
      2. 12.1.2 Block Diagram
    2. 12.2 Module Operation
      1. 12.2.1 Configuring DCC Counters
      2. 12.2.2 Single-Shot Measurement Mode
      3. 12.2.3 Continuous Monitoring Mode
      4. 12.2.4 Error Conditions
    3. 12.3 Interrupts
    4. 12.4 Software
      1. 12.4.1 DCC Registers to Driverlib Functions
      2. 12.4.2 DCC Examples
        1. 12.4.2.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 12.4.2.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 12.4.2.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 12.5 DCC Registers
      1. 12.5.1 DCC Base Address Table
      2. 12.5.2 DCC_REGS Registers
  15. 13Real-Time Direct Memory Access (RTDMA)
    1. 13.1  Introduction
      1. 13.1.1 Features
      2. 13.1.2 RTDMA Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2  RTDMA Trigger Source Options
    3. 13.3  RTDMA Bus
    4. 13.4  Address Pointer and Transfer Control
    5. 13.5  Pipeline Timing and Throughput
    6. 13.6  Channel Priority
      1. 13.6.1 Round-Robin Mode
      2. 13.6.2 Software Configurable Priority of Channels
    7. 13.7  Overrun Detection Feature
    8. 13.8  Burst Mode
    9. 13.9  Safety and Security
      1. 13.9.1 Safety
        1. 13.9.1.1 Lockstep Mode
        2. 13.9.1.2 Memory Protection Unit (MPU)
          1. 13.9.1.2.1 MPU Errors
      2. 13.9.2 Security
      3. 13.9.3 RTDMA Errors
      4. 13.9.4 Self-Test and Diagnostics
    10. 13.10 Software
      1. 13.10.1 RTDMA Registers to Driverlib Functions
      2. 13.10.2 RTDMA Examples
        1. 13.10.2.1 RTDMA Academy Lab - SINGLE_CORE
        2. 13.10.2.2 RTDMA Transfer - SINGLE_CORE
        3. 13.10.2.3 RTDMA Transfer with MPU - SINGLE_CORE
    11. 13.11 RTDMA Registers
      1. 13.11.1 RTDMA Base Address Table
      2. 13.11.2 RTDMA_REGS Registers
      3. 13.11.3 RTDMA_DIAG_REGS Registers
      4. 13.11.4 RTDMA_SELFTEST_REGS Registers
      5. 13.11.5 RTDMA_MPU_REGS Registers
      6. 13.11.6 RTDMA_CH_REGS Registers
  16. 14External Memory Interface (EMIF)
    1. 14.1 Introduction
      1. 14.1.1 Purpose of the Peripheral
      2. 14.1.2 Features
        1. 14.1.2.1 Asynchronous Memory Support
        2. 14.1.2.2 Synchronous DRAM Memory Support
      3. 14.1.3 Functional Block Diagram
      4. 14.1.4 Configuring Device Pins
    2. 14.2 EMIF Module Architecture
      1. 14.2.1  EMIF Clock Control
      2. 14.2.2  EMIF Requests
      3. 14.2.3  EMIF Signal Descriptions
      4. 14.2.4  EMIF Signal Multiplexing Control
      5. 14.2.5  SDRAM Controller and Interface
        1. 14.2.5.1  SDRAM Commands
        2. 14.2.5.2  Interfacing to SDRAM
        3. 14.2.5.3  SDRAM Configuration Registers
        4. 14.2.5.4  SDRAM Auto-Initialization Sequence
        5. 14.2.5.5  SDRAM Configuration Procedure
        6. 14.2.5.6  EMIF Refresh Controller
          1. 14.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 14.2.5.7  Self-Refresh Mode
        8. 14.2.5.8  Power-Down Mode
        9. 14.2.5.9  SDRAM Read Operation
        10. 14.2.5.10 SDRAM Write Operations
        11. 14.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 14.2.6  Asynchronous Controller and Interface
        1. 14.2.6.1 Interfacing to Asynchronous Memory
        2. 14.2.6.2 Accessing Larger Asynchronous Memories
        3. 14.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 14.2.6.4 Read and Write Operations in Normal Mode
          1. 14.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 14.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 14.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 14.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 14.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 14.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 14.2.7  Data Bus Parking
      8. 14.2.8  Reset and Initialization Considerations
      9. 14.2.9  Interrupt Support
        1. 14.2.9.1 Interrupt Events
      10. 14.2.10 RTDMA Event Support
      11. 14.2.11 EMIF Signal Multiplexing
      12. 14.2.12 Memory Map
      13. 14.2.13 Priority and Arbitration
      14. 14.2.14 System Considerations
        1. 14.2.14.1 Asynchronous Request Times
      15. 14.2.15 Power Management
        1. 14.2.15.1 Power Management Using Self-Refresh Mode
        2. 14.2.15.2 Power Management Using Power Down Mode
      16. 14.2.16 Emulation Considerations
    3. 14.3 EMIF Subsystem (EMIFSS)
      1. 14.3.1 Burst Support
      2. 14.3.2 EMIFSS Performance Improvement
      3. 14.3.3 Buffer Module
        1. 14.3.3.1 CPU Write FIFO
      4. 14.3.4 Emulation Mode
    4. 14.4 Example Configuration
      1. 14.4.1 Hardware Interface
      2. 14.4.2 Software Configuration
        1. 14.4.2.1 Configuring the SDRAM Interface
          1. 14.4.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 14.4.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 14.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 14.4.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 14.4.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 14.4.2.2 Configuring the Flash Interface
          1. 14.4.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    5. 14.5 Software
      1. 14.5.1 EMIF Registers to Driverlib Functions
      2. 14.5.2 EMIF Examples
    6. 14.6 EMIF Registers
      1. 14.6.1 EMIF Base Address Table
      2. 14.6.2 EMIF_REGS Registers
  17. 15General-Purpose Input/Output (GPIO)
    1. 15.1  Introduction
      1. 15.1.1 GPIO Related Collateral
    2. 15.2  Configuration Overview
    3. 15.3  Digital Inputs on ADC Pins (AIOs)
    4. 15.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 15.5  Digital General-Purpose I/O Control
    6. 15.6  Input Qualification
      1. 15.6.1 No Synchronization (Asynchronous Input)
      2. 15.6.2 Synchronization to SYSCLKOUT Only
      3. 15.6.3 Qualification Using a Sampling Window
    7. 15.7  PMBUS and I2C Signals
    8. 15.8  GPIO and Peripheral Muxing
      1. 15.8.1 GPIO Muxing
      2. 15.8.2 Peripheral Muxing
    9. 15.9  Internal Pullup Configuration Requirements
    10. 15.10 Software
      1. 15.10.1 GPIO Registers to Driverlib Functions
      2. 15.10.2 GPIO Examples
        1. 15.10.2.1 Device GPIO Toggle - SINGLE_CORE
        2. 15.10.2.2 XINT/XBAR example - SINGLE_CORE
      3. 15.10.3 LED Examples
        1. 15.10.3.1 LED Blinky Example - MULTI_CORE
        2. 15.10.3.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 15.10.3.3 LED Blinky example - SINGLE_CORE
        4. 15.10.3.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 15.10.3.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 15.10.3.6 LED Blinky Example (CPU3) - MULTI_CORE
    11. 15.11 GPIO Registers
      1. 15.11.1 GPIO Base Address Table
      2. 15.11.2 GPIO_CTRL_REGS Registers
      3. 15.11.3 GPIO_DATA_REGS Registers
      4. 15.11.4 GPIO_DATA_READ_REGS Registers
  18. 16Interprocessor Communication (IPC)
    1. 16.1 Introduction
    2. 16.2 IPC Flags and Interrupts
    3. 16.3 IPC Command Registers
    4. 16.4 Free-Running Counter
    5. 16.5 IPC Communication Protocol
    6. 16.6 Software
      1. 16.6.1 IPC Registers to Driverlib Functions
      2. 16.6.2 IPC Examples
        1. 16.6.2.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 16.6.2.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 16.6.2.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 16.6.2.4 IPC basic message passing example with interrupt - MULTI_CORE
    7. 16.7 IPC Registers
      1. 16.7.1 IPC Base Address Table
      2. 16.7.2 IPC_COUNTER_REGS Registers
      3. 16.7.3 CPU1_IPC_SEND_REGS Registers
      4. 16.7.4 CPU2_IPC_SEND_REGS Registers
      5. 16.7.5 CPU3_IPC_SEND_REGS Registers
      6. 16.7.6 CPU1_IPC_RCV_REGS Registers
      7. 16.7.7 CPU2_IPC_RCV_REGS Registers
      8. 16.7.8 CPU3_IPC_RCV_REGS Registers
  19. 17Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 17.1 Introduction
    2. 17.2 Enhanced Bus Comparator Unit
      1. 17.2.1 Enhanced Bus Comparator Unit Operations
      2. 17.2.2 Stack Qualification
      3. 17.2.3 Event Masking and Exporting
    3. 17.3 System Event Counter Unit
      1. 17.3.1 System Event Counter Modes
        1. 17.3.1.1 Counting Active Levels Versus Edges
        2. 17.3.1.2 Max and Min Mode
        3. 17.3.1.3 Cumulative Mode
        4. 17.3.1.4 Input Signal Selection
      2. 17.3.2 Reset on Event
      3. 17.3.3 Operation Conditions
    4. 17.4 Program Counter Trace
      1. 17.4.1 Functional Block Diagram
      2. 17.4.2 Trace Qualification Modes
        1. 17.4.2.1 Trace Input Signal Conditioning
      3. 17.4.3 Trace Memory
      4. 17.4.4 PC Trace Software Operation
      5. 17.4.5 Trace Operation in Debug Mode
    5. 17.5 ERAD Ownership, Initialization, and Reset
      1. 17.5.1 Feature Level Ownership
      2. 17.5.2 Feature Access Security Mechanism
      3. 17.5.3 PC Trace Access Security Mechanism
    6. 17.6 ERAD Programming Sequence
      1. 17.6.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 17.6.2 Timer and Counter Programming Sequence
    7. 17.7 Software
      1. 17.7.1 ERAD Registers to Driverlib Functions
    8. 17.8 ERAD Registers
      1. 17.8.1 ERAD Base Address Table
        1. 17.8.1.1 ERAD_REGS Registers
  20. 18Data Logger and Trace (DLT)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 DLT Related Collateral
      3. 18.1.3 Interfaces
        1. 18.1.3.1 Block Diagram
    2. 18.2 Functional Overview
      1. 18.2.1 DLT Configuration
        1. 18.2.1.1 LINK Filter
        2. 18.2.1.2 TAG Filter
        3. 18.2.1.3 ERAD Event Trigger
        4. 18.2.1.4 Concurrent FILTERING modes
      2. 18.2.2 Time-stamping
      3. 18.2.3 FIFO Construction
        1. 18.2.3.1 FIFO Interrupt
    3. 18.3 Software
      1. 18.3.1 DLT Registers to Driverlib Functions
      2. 18.3.2 DLT Examples
        1. 18.3.2.1 DLT TAG filter example - SINGLE_CORE
        2. 18.3.2.2 DLT TAG filter example - SINGLE_CORE
        3. 18.3.2.3 DLT ERAD filter example - SINGLE_CORE
    4. 18.4 DLT Registers
      1. 18.4.1 DLT Base Address Table
      2. 18.4.2 DLT_CORE_REGS Registers
      3. 18.4.3 DLT_FIFO_REGS Registers
  21. 19Waveform Analyzer Diagnostic (WADI)
    1. 19.1 WADI Overview
      1. 19.1.1 Features
      2. 19.1.2 WADI Related Collateral
      3. 19.1.3 Block Diagram
      4. 19.1.4 Description
    2. 19.2 Signal and Trigger Input Configuration
      1. 19.2.1 SIG1 and SIG2 Configuration
      2. 19.2.2 Trigger 1 and Trigger 2
    3. 19.3 WADI Block
      1. 19.3.1 Overview
      2. 19.3.2 Counters
      3. 19.3.3 Pulse Width
        1. 19.3.3.1 Pulse Width Single Measurement
        2. 19.3.3.2 Pulse Width Aggregation
        3. 19.3.3.3 Pulse Width Average and Peak
      4. 19.3.4 Edge Count
        1. 19.3.4.1 Edge Count with Fixed Window
        2. 19.3.4.2 Edge Count with Moving Window
      5. 19.3.5 Signal1 to Signal2 Comparison
      6. 19.3.6 Dead Band and Phase
      7. 19.3.7 Simultaneous Measurement
    4. 19.4 Safe State Sequencer (SSS)
      1. 19.4.1 SSS Configuration
    5. 19.5 Lock and Commit Registers
    6. 19.6 Interrupt and Error Handling
    7. 19.7 RTDMA Interfaces
      1. 19.7.1 RTDMA Trigger
    8. 19.8 Software
      1. 19.8.1 WADI Registers to Driverlib Functions
      2. 19.8.2 WADI Examples
        1. 19.8.2.1 WADI Duty and Frequency check - SINGLE_CORE
    9. 19.9 WADI Registers
      1. 19.9.1 WADI Base Address Table
      2. 19.9.2 WADI_CONFIG_REGS Registers
      3. 19.9.3 WADI_OPER_SSS_REGS Registers
  22. 20Crossbar (X-BAR)
    1. 20.1 X-BAR Related Collateral
    2. 20.2 Input X-BAR, ICL XBAR, MINDB XBAR,
      1. 20.2.1 ICL and MINDB X-BAR
    3. 20.3 ePWM , CLB, and GPIO Output X-BAR
      1. 20.3.1 ePWM X-BAR
        1. 20.3.1.1 ePWM X-BAR Architecture
      2. 20.3.2 CLB X-BAR
        1. 20.3.2.1 CLB X-BAR Architecture
      3. 20.3.3 GPIO Output X-BAR
        1. 20.3.3.1 GPIO Output X-BAR Architecture
      4. 20.3.4 X-BAR Flags
    4. 20.4 Software
      1. 20.4.1 INPUT_XBAR Registers to Driverlib Functions
      2. 20.4.2 EPWM_XBAR Registers to Driverlib Functions
      3. 20.4.3 CLB_XBAR Registers to Driverlib Functions
      4. 20.4.4 OUTPUT_XBAR Registers to Driverlib Functions
      5. 20.4.5 MDL_XBAR Registers to Driverlib Functions
      6. 20.4.6 ICL_XBAR Registers to Driverlib Functions
      7. 20.4.7 XBAR Registers to Driverlib Functions
      8. 20.4.8 XBAR Examples
        1. 20.4.8.1 Input XBAR to Output XBAR Connection - SINGLE_CORE
        2. 20.4.8.2 Output XBAR Pulse Stretch - SINGLE_CORE
    5. 20.5 XBAR Registers
      1. 20.5.1 XBAR Base Address Table
      2. 20.5.2 INPUT_XBAR_REGS Registers
      3. 20.5.3 EPWM_XBAR_REGS Registers
      4. 20.5.4 CLB_XBAR_REGS Registers
      5. 20.5.5 OUTPUTXBAR_REGS Registers
      6. 20.5.6 MDL_XBAR_REGS Registers
      7. 20.5.7 ICL_XBAR_REGS Registers
      8. 20.5.8 OUTPUTXBAR_FLAG_REGS Registers
      9. 20.5.9 XBAR_REGS Registers
  23. 21Embedded Pattern Generator (EPG)
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 EPG Block Diagram
      3. 21.1.3 EPG Related Collateral
    2. 21.2 Clock Generator Modules
      1. 21.2.1 DCLK (50% duty cycle clock)
      2. 21.2.2 Clock Stop
    3. 21.3 Signal Generator Module
    4. 21.4 EPG Peripheral Signal Mux Selection
    5. 21.5 Application Software Notes
    6. 21.6 EPG Example Use Cases
      1. 21.6.1 EPG Example: Synchronous Clocks with Offset
        1. 21.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 21.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 21.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 21.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 21.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 21.6.4 EPG Example: Clock and Data Pair
        1. 21.6.4.1 Clock and Data Pair Register Configuration
      5. 21.6.5 EPG Example: Clock and Skewed Data Pair
        1. 21.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 21.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 21.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 21.7 EPG Interrupt
    8. 21.8 Software
      1. 21.8.1 EPG Registers to Driverlib Functions
      2. 21.8.2 EPG Examples
        1. 21.8.2.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 21.8.2.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 21.8.2.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 21.8.2.4 EPG Generate Serial Data - SINGLE_CORE
        5. 21.8.2.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 21.9 EPG Registers
      1. 21.9.1 EPG Base Address Table
      2. 21.9.2 EPG_REGS Registers
      3. 21.9.3 EPG_MUX_REGS Registers
  24. 22â–º ANALOG PERIPHERALS
    1.     Technical Reference Manual Overview
  25. 23Analog Subsystem
    1. 23.1 Introduction
      1. 23.1.1 Features
      2. 23.1.2 Block Diagram
    2. 23.2 Optimizing Power-Up Time
    3. 23.3 Digital Inputs on ADC Pins (AIOs)
    4. 23.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 23.5 Analog Pins and Internal Connections
    6. 23.6 Software
      1. 23.6.1 ASYSCTL Registers to Driverlib Functions
    7. 23.7 Lock Registers
    8. 23.8 ASBSYS Registers
      1. 23.8.1 ASBSYS Base Address Table
      2. 23.8.2 ANALOG_SUBSYS_REGS Registers
  26. 24Analog-to-Digital Converter (ADC)
    1. 24.1  Introduction
      1. 24.1.1 ADC Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Block Diagram
    2. 24.2  ADC Configurability
      1. 24.2.1 Clock Configuration
      2. 24.2.2 Resolution
      3. 24.2.3 Voltage Reference
        1. 24.2.3.1 External Reference Mode
        2. 24.2.3.2 Internal Reference Mode
        3. 24.2.3.3 Ganged References
        4. 24.2.3.4 Selecting Reference Mode
      4. 24.2.4 Signal Mode
      5. 24.2.5 Expected Conversion Results
      6. 24.2.6 Interpreting Conversion Results
    3. 24.3  SOC Principle of Operation
      1. 24.3.1 SOC Configuration
      2. 24.3.2 Trigger Operation
        1. 24.3.2.1 Global Software Trigger
        2. 24.3.2.2 Trigger Repeaters
          1. 24.3.2.2.1 Oversampling Mode
          2. 24.3.2.2.2 Undersampling Mode
          3. 24.3.2.2.3 Trigger Phase Delay
          4. 24.3.2.2.4 Re-trigger Spread
          5. 24.3.2.2.5 Trigger Repeater Configuration
            1. 24.3.2.2.5.1 Register Shadow Updates
          6. 24.3.2.2.6 Re-Trigger Logic
          7. 24.3.2.2.7 Multi-Path Triggering Behavior
      3. 24.3.3 ADC Acquisition (Sample and Hold) Window
      4. 24.3.4 ADC Input Models
      5. 24.3.5 Channel Selection
        1. 24.3.5.1 External Channel Selection
          1. 24.3.5.1.1 External Channel Selection Timing
    4. 24.4  SOC Configuration Examples
      1. 24.4.1 Single Conversion from ePWM Trigger
      2. 24.4.2 Oversampled Conversion from ePWM Trigger
      3. 24.4.3 Multiple Conversions from CPU Timer Trigger
      4. 24.4.4 Software Triggering of SOCs
    5. 24.5  ADC Conversion Priority
    6. 24.6  Burst Mode
      1. 24.6.1 Burst Mode Example
      2. 24.6.2 Burst Mode Priority Example
    7. 24.7  EOC and Interrupt Operation
      1. 24.7.1 Interrupt Overflow
      2. 24.7.2 Continue to Interrupt Mode
      3. 24.7.3 Early Interrupt Configuration Mode
    8. 24.8  Post-Processing Blocks
      1. 24.8.1 PPB Offset Correction
      2. 24.8.2 PPB Error Calculation
      3. 24.8.3 PPB Result Delta Calculation
      4. 24.8.4 PPB Limit Detection and Zero-Crossing Detection
        1. 24.8.4.1 PPB Digital Trip Filter
      5. 24.8.5 PPB Sample Delay Capture
      6. 24.8.6 PPB Oversampling
        1. 24.8.6.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 24.8.6.2 Outlier Rejection
    9. 24.9  Result Safety Checker
      1. 24.9.1 Result Safety Checker Operation
      2. 24.9.2 Result Safety Checker Interrupts and Events
    10. 24.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 24.10.1 Implementation
      2. 24.10.2 Detecting an Open Input Pin
      3. 24.10.3 Detecting a Shorted Input Pin
    11. 24.11 Power-Up Sequence
    12. 24.12 ADC Calibration
      1. 24.12.1 ADC Zero Offset Calibration
    13. 24.13 ADC Timings
      1. 24.13.1 ADC Timing Diagrams
      2. 24.13.2 Post-Processing Block Timings
    14. 24.14 Additional Information
      1. 24.14.1 Ensuring Synchronous Operation
        1. 24.14.1.1 Basic Synchronous Operation
        2. 24.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 24.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 24.14.1.4 Synchronous Operation with Different Resolutions
        5. 24.14.1.5 Non-overlapping Conversions
      2. 24.14.2 Choosing an Acquisition Window Duration
      3. 24.14.3 Achieving Simultaneous Sampling
      4. 24.14.4 Result Register Mapping
      5. 24.14.5 Internal Temperature Sensor
      6. 24.14.6 Designing an External Reference Circuit
      7. 24.14.7 Internal Test Mode
      8. 24.14.8 ADC Gain and Offset Calibration
    15. 24.15 Software
      1. 24.15.1 ADC Registers to Driverlib Functions
      2. 24.15.2 ADC Examples
        1. 24.15.2.1  ADC Software Triggering - SINGLE_CORE
        2. 24.15.2.2  ADC ePWM Triggering - SINGLE_CORE
        3. 24.15.2.3  ADC Temperature Sensor Conversion - SINGLE_CORE
        4. 24.15.2.4  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        5. 24.15.2.5  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        6. 24.15.2.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        7. 24.15.2.7  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        8. 24.15.2.8  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        9. 24.15.2.9  ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        10. 24.15.2.10 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        11. 24.15.2.11 ADC Burst Mode - SINGLE_CORE
        12. 24.15.2.12 ADC Burst Mode Oversampling - SINGLE_CORE
        13. 24.15.2.13 ADC SOC Oversampling - SINGLE_CORE
        14. 24.15.2.14 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        15. 24.15.2.15 ADC Trigger Repeater Oversampling - SINGLE_CORE
        16. 24.15.2.16 ADC Trigger Repeater Undersampling - SINGLE_CORE
        17. 24.15.2.17 ADC Safety Checker - SINGLE_CORE
    16. 24.16 ADC Registers
      1. 24.16.1 ADC Base Address Table
      2. 24.16.2 ADC_RESULT_REGS Registers
      3. 24.16.3 ADC_REGS Registers
      4. 24.16.4 ADC_SAFECHECK_REGS Registers
      5. 24.16.5 ADC_SAFECHECK_INTEVT_REGS Registers
      6. 24.16.6 ADC_GLOBAL_REGS Registers
  27. 25Buffered Digital-to-Analog Converter (DAC)
    1. 25.1 Introduction
      1. 25.1.1 DAC Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
    2. 25.2 Using the DAC
      1. 25.2.1 Initialization Sequence
      2. 25.2.2 DAC Offset Adjustment
      3. 25.2.3 EPWMSYNCPER Signal
    3. 25.3 Lock Registers
    4. 25.4 Software
      1. 25.4.1 DAC Registers to Driverlib Functions
      2. 25.4.2 DAC Examples
        1. 25.4.2.1 Buffered DAC Enable - SINGLE_CORE
        2. 25.4.2.2 Buffered DAC Random - SINGLE_CORE
    5. 25.5 DAC Registers
      1. 25.5.1 DAC Base Address Table
      2. 25.5.2 DAC_REGS Registers
  28. 26Comparator Subsystem (CMPSS)
    1. 26.1 Introduction
      1. 26.1.1 CMPSS Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Block Diagram
    2. 26.2 Comparator
    3. 26.3 Reference DAC
    4. 26.4 Ramp Generator
      1. 26.4.1 Ramp Generator Overview
      2. 26.4.2 Ramp Generator Behavior
      3. 26.4.3 Ramp Generator Behavior at Corner Cases
    5. 26.5 Digital Filter
      1. 26.5.1 Filter Initialization Sequence
    6. 26.6 Using the CMPSS
      1. 26.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 26.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 26.6.3 Calibrating the CMPSS
      4. 26.6.4 Enabling and Disabling the CMPSS Clock
    7. 26.7 Software
      1. 26.7.1 CMPSS Registers to Driverlib Functions
      2. 26.7.2 CMPSS Examples
        1. 26.7.2.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 26.7.2.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 26.8 CMPSS Registers
      1. 26.8.1 CMPSS Base Address Table
      2. 26.8.2 CMPSS_REGS Registers
  29. 27â–º CONTROL PERIPHERALS
    1.     Technical Reference Manual Overview
  30. 28Enhanced Capture (eCAP)
    1. 28.1 Introduction
      1. 28.1.1 Features
      2. 28.1.2 ECAP Related Collateral
    2. 28.2 Description
    3. 28.3 Configuring Device Pins for the eCAP
    4. 28.4 Capture and APWM Operating Mode
    5. 28.5 Capture Mode Description
      1. 28.5.1  Event Prescaler
      2. 28.5.2  Glitch Filter
      3. 28.5.3  Edge Polarity Select and Qualifier
      4. 28.5.4  Continuous/One-Shot Control
      5. 28.5.5  32-Bit Counter and Phase Control
      6. 28.5.6  CAP1-CAP4 Registers
      7. 28.5.7  eCAP Synchronization
        1. 28.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 28.5.8  Interrupt Control
      9. 28.5.9  RTDMA Interrupt
      10. 28.5.10 ADC SOC Event
      11. 28.5.11 Shadow Load and Lockout Control
      12. 28.5.12 APWM Mode Operation
      13. 28.5.13 Signal Monitoring Unit
        1. 28.5.13.1 Pulse Width and Period Monitoring
        2. 28.5.13.2 Edge Monitoring
    6. 28.6 Application of the eCAP Module
      1. 28.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 28.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 28.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 28.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 28.7 Application of the APWM Mode
      1. 28.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 28.8 Software
      1. 28.8.1 ECAP Registers to Driverlib Functions
      2. 28.8.2 ECAP Examples
        1. 28.8.2.1 eCAP APWM Example - SINGLE_CORE
        2. 28.8.2.2 eCAP Capture PWM Example - SINGLE_CORE
        3. 28.8.2.3 eCAP APWM Phase-shift Example - SINGLE_CORE
    9. 28.9 ECAP Registers
      1. 28.9.1 ECAP Base Address Table
      2. 28.9.2 ECAP_REGS Registers
      3. 28.9.3 ECAP_SIGNAL_MONITORING Registers
      4. 28.9.4 HRCAP_REGS Registers
  31. 29High Resolution Capture (HRCAP)
    1. 29.1 Introduction
      1. 29.1.1 HRCAP Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Description
    2. 29.2 Operational Details
      1. 29.2.1 HRCAP Clocking
      2. 29.2.2 HRCAP Initialization Sequence
      3. 29.2.3 HRCAP Interrupts
      4. 29.2.4 HRCAP Calibration
        1. 29.2.4.1 Applying the Scale Factor
    3. 29.3 Known Exceptions
    4. 29.4 Software
      1. 29.4.1 HRCAP Examples
        1. 29.4.1.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    5. 29.5 HRCAP Registers
      1. 29.5.1 HRCAP Base Address Table
      2. 29.5.2 HRCAP_REGS Registers
  32. 30Enhanced Pulse Width Modulator (ePWM)
    1. 30.1  Introduction
      1. 30.1.1 EPWM Related Collateral
      2. 30.1.2 Submodule Overview
    2. 30.2  Configuring Device Pins
    3. 30.3  ePWM Modules Overview
    4. 30.4  Time-Base (TB) Submodule
      1. 30.4.1 Purpose of the Time-Base Submodule
      2. 30.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 30.4.3 Calculating PWM Period and Frequency
        1. 30.4.3.1 Time-Base Period Shadow Register
        2. 30.4.3.2 Time-Base Clock Synchronization
        3. 30.4.3.3 Time-Base Counter Synchronization
        4. 30.4.3.4 ePWM SYNC Selection
      4. 30.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 30.4.5 Simultaneous Writes Between ePWM Register Instances
      6. 30.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 30.4.7 Global Load
        1. 30.4.7.1 Global Load Pulse Pre-Scalar
        2. 30.4.7.2 One-Shot Load Mode
        3. 30.4.7.3 One-Shot Sync Mode
    5. 30.5  Counter-Compare (CC) Submodule
      1. 30.5.1 Purpose of the Counter-Compare Submodule
      2. 30.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 30.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 30.5.4 Count Mode Timing Waveforms
    6. 30.6  Action-Qualifier (AQ) Submodule
      1. 30.6.1 Purpose of the Action-Qualifier Submodule
      2. 30.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 30.6.3 Action-Qualifier Event Priority
      4. 30.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 30.6.5 Configuration Requirements for Common Waveforms
    7. 30.7  XCMP Complex Waveform Generator Mode
      1. 30.7.1 XCMP Allocation to CMPA and CMPB
      2. 30.7.2 XCMP Shadow Buffers
      3. 30.7.3 XCMP Operation
    8. 30.8  Dead-Band Generator (DB) Submodule
      1. 30.8.1 Purpose of the Dead-Band Submodule
      2. 30.8.2 Dead-band Submodule Additional Operating Modes
      3. 30.8.3 Operational Highlights for the Dead-Band Submodule
    9. 30.9  PWM Chopper (PC) Submodule
      1. 30.9.1 Purpose of the PWM Chopper Submodule
      2. 30.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 30.9.3 Waveforms
        1. 30.9.3.1 One-Shot Pulse
        2. 30.9.3.2 Duty Cycle Control
    10. 30.10 Trip-Zone (TZ) Submodule
      1. 30.10.1 Purpose of the Trip-Zone Submodule
      2. 30.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 30.10.2.1 Trip-Zone Configurations
      3. 30.10.3 Generating Trip Event Interrupts
    11. 30.11 Diode Emulation (DE) Submodule
      1. 30.11.1 DEACTIVE Mode
      2. 30.11.2 Exiting DE Mode
      3. 30.11.3 Re-Entering DE Mode
      4. 30.11.4 DE Monitor
    12. 30.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 30.12.1 Minimum Dead-Band (MINDB)
      2. 30.12.2 Illegal Combo Logic (ICL)
    13. 30.13 Event-Trigger (ET) Submodule
      1. 30.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 30.14 Digital Compare (DC) Submodule
      1. 30.14.1 Purpose of the Digital Compare Submodule
      2. 30.14.2 Enhanced Trip Action Using CMPSS
      3. 30.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 30.14.4 Operation Highlights of the Digital Compare Submodule
        1. 30.14.4.1 Digital Compare Events
        2. 30.14.4.2 Event Filtering
        3. 30.14.4.3 Valley Switching
        4. 30.14.4.4 Event Detection
          1. 30.14.4.4.1 Input Signal Detection
          2. 30.14.4.4.2 MIN and MAX Detection Circuit
    15. 30.15 ePWM Crossbar (X-BAR)
    16. 30.16 Applications to Power Topologies
      1. 30.16.1  Overview of Multiple Modules
      2. 30.16.2  Key Configuration Capabilities
      3. 30.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 30.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 30.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 30.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 30.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 30.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 30.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 30.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 30.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 30.17 Register Lock Protection
    18. 30.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 30.18.1 Operational Description of HRPWM
        1. 30.18.1.1 Controlling the HRPWM Capabilities
        2. 30.18.1.2 HRPWM Source Clock
        3. 30.18.1.3 Configuring the HRPWM
        4. 30.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 30.18.1.5 Principle of Operation
          1. 30.18.1.5.1 Edge Positioning
          2. 30.18.1.5.2 Scaling Considerations
          3. 30.18.1.5.3 Duty Cycle Range Limitation
          4. 30.18.1.5.4 High-Resolution Period
            1. 30.18.1.5.4.1 High-Resolution Period Configuration
        6. 30.18.1.6 Deadband High-Resolution Operation
        7. 30.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 30.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 30.18.1.8.1 #Defines for HRPWM Header Files
          2. 30.18.1.8.2 Implementing a Simple Buck Converter
            1. 30.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 30.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 30.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 30.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 30.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 30.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 30.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 30.18.2.2 Software Usage
          1. 30.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1131
          3. 30.18.2.2.2 Declaring an Element
          4.        1133
          5. 30.18.2.2.3 Initializing With a Scale Factor Value
          6.        1135
          7. 30.18.2.2.4 SFO Function Calls
    19. 30.19 Software
      1. 30.19.1 EPWM Registers to Driverlib Functions
      2. 30.19.2 HRPWMCAL Registers to Driverlib Functions
      3. 30.19.3 EPWM Examples
        1. 30.19.3.1  ePWM Trip Zone - SINGLE_CORE
        2. 30.19.3.2  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        3. 30.19.3.3  ePWM Synchronization - SINGLE_CORE
        4. 30.19.3.4  ePWM Digital Compare - SINGLE_CORE
        5. 30.19.3.5  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        6. 30.19.3.6  ePWM Valley Switching - SINGLE_CORE
        7. 30.19.3.7  ePWM Digital Compare Edge Filter - SINGLE_CORE
        8. 30.19.3.8  ePWM Deadband - SINGLE_CORE
        9. 30.19.3.9  ePWM DMA - SINGLE_CORE
        10. 30.19.3.10 ePWM Chopper - SINGLE_CORE
        11. 30.19.3.11 EPWM Configure Signal - SINGLE_CORE
        12. 30.19.3.12 Realization of Monoshot mode - SINGLE_CORE
        13. 30.19.3.13 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        14. 30.19.3.14 ePWM XCMP Mode - SINGLE_CORE
        15. 30.19.3.15 ePWM Event Detection - SINGLE_CORE
    20. 30.20 EPWM Registers
      1. 30.20.1 EPWM Base Address Table
      2. 30.20.2 EPWM_REGS Registers
      3. 30.20.3 EPWM_XCMP_REGS Registers
      4. 30.20.4 DE_REGS Registers
      5. 30.20.5 MINDB_LUT_REGS Registers
      6. 30.20.6 HRPWMCAL_REGS Registers
  33. 31Enhanced Quadrature Encoder Pulse (eQEP)
    1. 31.1  Introduction
      1. 31.1.1 EQEP Related Collateral
    2. 31.2  Configuring Device Pins
    3. 31.3  Description
      1. 31.3.1 EQEP Inputs
      2. 31.3.2 Functional Description
      3. 31.3.3 eQEP Memory Map
    4. 31.4  Quadrature Decoder Unit (QDU)
      1. 31.4.1 Position Counter Input Modes
        1. 31.4.1.1 Quadrature Count Mode
        2. 31.4.1.2 Direction-Count Mode
        3. 31.4.1.3 Up-Count Mode
        4. 31.4.1.4 Down-Count Mode
      2. 31.4.2 eQEP Input Polarity Selection
      3. 31.4.3 Position-Compare Sync Output
    5. 31.5  Position Counter and Control Unit (PCCU)
      1. 31.5.1 Position Counter Operating Modes
        1. 31.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 31.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 31.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 31.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 31.5.2 Position Counter Latch
        1. 31.5.2.1 Index Event Latch
        2. 31.5.2.2 Strobe Event Latch
      3. 31.5.3 Position Counter Initialization
      4. 31.5.4 eQEP Position-compare Unit
    6. 31.6  eQEP Edge Capture Unit
    7. 31.7  eQEP Watchdog
    8. 31.8  eQEP Unit Timer Base
    9. 31.9  QMA Module
      1. 31.9.1 Modes of Operation
        1. 31.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 31.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 31.9.2 Interrupt and Error Generation
    10. 31.10 eQEP Interrupt Structure
    11. 31.11 Software
      1. 31.11.1 EQEP Registers to Driverlib Functions
      2. 31.11.2 EQEP Examples
        1. 31.11.2.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 31.11.2.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 31.12 EQEP Registers
      1. 31.12.1 EQEP Base Address Table
      2. 31.12.2 EQEP_REGS Registers
  34. 32Sigma Delta Filter Module (SDFM)
    1. 32.1  Introduction
      1. 32.1.1 SDFM Related Collateral
      2. 32.1.2 Features
      3. 32.1.3 Block Diagram
    2. 32.2  Configuring Device Pins
    3. 32.3  Input Qualification
    4. 32.4  Input Control Unit
    5. 32.5  SDFM Clock Control
    6. 32.6  Sinc Filter
      1. 32.6.1 Data Rate and Latency of the Sinc Filter
    7. 32.7  Data (Primary) Filter Unit
      1. 32.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 32.7.2 Data FIFO
      3. 32.7.3 SDSYNC Event
    8. 32.8  Comparator (Secondary) Filter Unit
      1. 32.8.1 Higher Threshold (HLT) Comparators
      2. 32.8.2 Lower Threshold (LLT) Comparators
      3. 32.8.3 Digital Filter
    9. 32.9  Theoretical SDFM Filter Output
    10. 32.10 Interrupt Unit
      1. 32.10.1 SDFM (SDyERR) Interrupt Sources
      2. 32.10.2 Data Ready (DRINT) Interrupt Sources
    11. 32.11 Software
      1. 32.11.1 SDFM Registers to Driverlib Functions
      2. 32.11.2 SDFM Examples
    12. 32.12 SDFM Registers
      1. 32.12.1 SDFM Base Address Table
      2. 32.12.2 SDFM_REGS Registers
  35. 33â–º COMMUNICATION PERIPHERALS
    1.     Technical Reference Manual Overview
  36. 34Modular Controller Area Network (MCAN)
    1. 34.1 MCAN Introduction
      1. 34.1.1 MCAN Related Collateral
      2. 34.1.2 MCAN Features
    2. 34.2 MCAN Environment
    3. 34.3 CAN Network Basics
    4. 34.4 MCAN Integration
    5. 34.5 MCAN Functional Description
      1. 34.5.1  Module Clocking Requirements
      2. 34.5.2  Interrupt Requests
      3. 34.5.3  Operating Modes
        1. 34.5.3.1 Software Initialization
        2. 34.5.3.2 Normal Operation
        3. 34.5.3.3 CAN FD Operation
      4. 34.5.4  Transmitter Delay Compensation
        1. 34.5.4.1 Description
        2. 34.5.4.2 Transmitter Delay Compensation Measurement
      5. 34.5.5  Restricted Operation Mode
      6. 34.5.6  Bus Monitoring Mode
      7. 34.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 34.5.7.1 Frame Transmission in DAR Mode
      8. 34.5.8  Clock Stop Mode
        1. 34.5.8.1 Suspend Mode
        2. 34.5.8.2 Wakeup Request
      9. 34.5.9  Test Modes
        1. 34.5.9.1 External Loop Back Mode
        2. 34.5.9.2 Internal Loop Back Mode
      10. 34.5.10 Timestamp Generation
        1. 34.5.10.1 External Timestamp Counter
      11. 34.5.11 Timeout Counter
      12. 34.5.12 Safety
        1. 34.5.12.1 ECC Wrapper
        2. 34.5.12.2 ECC Aggregator
          1. 34.5.12.2.1 ECC Aggregator Overview
          2. 34.5.12.2.2 ECC Aggregator Registers
        3. 34.5.12.3 Reads to ECC Control and Status Registers
        4. 34.5.12.4 ECC Interrupts
      13. 34.5.13 Rx Handling
        1. 34.5.13.1 Acceptance Filtering
          1. 34.5.13.1.1 Range Filter
          2. 34.5.13.1.2 Filter for Specific IDs
          3. 34.5.13.1.3 Classic Bit Mask Filter
          4. 34.5.13.1.4 Standard Message ID Filtering
          5. 34.5.13.1.5 Extended Message ID Filtering
        2. 34.5.13.2 Rx FIFOs
          1. 34.5.13.2.1 Rx FIFO Blocking Mode
          2. 34.5.13.2.2 Rx FIFO Overwrite Mode
        3. 34.5.13.3 Dedicated Rx Buffers
          1. 34.5.13.3.1 Rx Buffer Handling
      14. 34.5.14 Tx Handling
        1. 34.5.14.1 Transmit Pause
        2. 34.5.14.2 Dedicated Tx Buffers
        3. 34.5.14.3 Tx FIFO
        4. 34.5.14.4 Tx Queue
        5. 34.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 34.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 34.5.14.7 Transmit Cancellation
        8. 34.5.14.8 Tx Event Handling
      15. 34.5.15 FIFO Acknowledge Handling
      16. 34.5.16 Message RAM
        1. 34.5.16.1 Message RAM Configuration
        2. 34.5.16.2 Rx Buffer and FIFO Element
        3. 34.5.16.3 Tx Buffer Element
        4. 34.5.16.4 Tx Event FIFO Element
        5. 34.5.16.5 Standard Message ID Filter Element
        6. 34.5.16.6 Extended Message ID Filter Element
    6. 34.6 Software
      1. 34.6.1 MCAN Examples
        1. 34.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 34.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
        3. 34.6.1.3 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
    7. 34.7 MCAN Registers
      1. 34.7.1 MCAN Base Address Table
      2. 34.7.2 MCANSS_REGS Registers
      3. 34.7.3 MCAN_REGS Registers
      4. 34.7.4 MCAN_ERROR_REGS Registers
  37. 35EtherCAT® SubordinateDevice Controller (ESC)
    1. 35.1 Introduction
      1. 35.1.1  EtherCAT Related Collateral
      2. 35.1.2  ESC Features
      3. 35.1.3  ESC Subsystem Integrated Features
      4. 35.1.4  ESC versus Beckhoff ET1100
      5. 35.1.5  EtherCAT IP Block Diagram
      6. 35.1.6  ESC Functional Blocks
        1. 35.1.6.1  Interface to EtherCAT MainDevice
        2. 35.1.6.2  Process Data Interface
        3. 35.1.6.3  General-Purpose Inputs and Outputs
        4. 35.1.6.4  EtherCAT Processing Unit (EPU)
        5. 35.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 35.1.6.6  Sync Manager
        7. 35.1.6.7  Monitoring
        8. 35.1.6.8  Reset Controller
        9. 35.1.6.9  PHY Management
        10. 35.1.6.10 Distributed Clock (DC)
        11. 35.1.6.11 EEPROM
        12. 35.1.6.12 Status / LEDs
      7. 35.1.7  EtherCAT Physical Layer
        1. 35.1.7.1 MII Interface
        2. 35.1.7.2 PHY Management Interface
          1. 35.1.7.2.1 PHY Address Configuration
          2. 35.1.7.2.2 PHY Reset Signal
          3. 35.1.7.2.3 PHY Clock
      8. 35.1.8  EtherCAT Protocol
      9. 35.1.9  EtherCAT State Machine (ESM)
      10. 35.1.10 More Information on EtherCAT
      11. 35.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 35.2 ESC and ESCSS Description
      1. 35.2.1  ESC RAM Parity and Memory Address Maps
        1. 35.2.1.1 ESC RAM Parity Logic
        2. 35.2.1.2 CPU1 ESC Memory Address Map
        3. 35.2.1.3 CPU2 ESC Memory Address Map
      2. 35.2.2  Local Host Communication
        1. 35.2.2.1 Byte Accessibility Through PDI
        2. 35.2.2.2 Software Details for Operation Across Clock Domains
      3. 35.2.3  Debug Emulation Mode Operation
      4. 35.2.4  ESC SubSystem
        1. 35.2.4.1 CPU1 Bus Interface
        2. 35.2.4.2 CPU2/CPU3 Bus Interface
      5. 35.2.5  Interrupts and Interrupt Mapping
      6. 35.2.6  Power, Clocks, and Resets
        1. 35.2.6.1 Power
        2. 35.2.6.2 Clocking
        3. 35.2.6.3 Resets
          1. 35.2.6.3.1 Chip-Level Reset
          2. 35.2.6.3.2 EtherCAT Soft Resets
          3. 35.2.6.3.3 Reset Out (RESET_OUT)
      7. 35.2.7  LED Controls
      8. 35.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 35.2.9  General-Purpose Inputs and Outputs
        1. 35.2.9.1 General-Purpose Inputs
        2. 35.2.9.2 General-Purpose Output
      10. 35.2.10 Distributed Clocks – Sync and Latch
        1. 35.2.10.1 Clock Synchronization
        2. 35.2.10.2 SYNC Signals
          1. 35.2.10.2.1 Seeking Host Intervention
        3. 35.2.10.3 LATCH Signals
          1. 35.2.10.3.1 Timestamping
        4. 35.2.10.4 Device Control and Synchronization
          1. 35.2.10.4.1 Synchronization of PWM
          2. 35.2.10.4.2 ECAP SYNC Inputs
          3. 35.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 35.3 Software Initialization Sequence and Allocating Ownership
    4. 35.4 ESC Configuration Constants
    5. 35.5 Software
      1. 35.5.1 ECAT_SS Registers to Driverlib Functions
      2. 35.5.2 ETHERNET Examples
    6. 35.6 ETHERCAT Registers
      1. 35.6.1 ETHERCAT Base Address Table
      2. 35.6.2 ESCSS_REGS Registers
      3. 35.6.3 ESCSS_CONFIG_REGS Registers
  38. 36Fast Serial Interface (FSI)
    1. 36.1 Introduction
      1. 36.1.1 FSI Related Collateral
      2. 36.1.2 FSI Features
    2. 36.2 System-level Integration
      1. 36.2.1 CPU Interface
      2. 36.2.2 Signal Description
        1. 36.2.2.1 Configuring Device Pins
      3. 36.2.3 FSI Interrupts
        1. 36.2.3.1 Transmitter Interrupts
        2. 36.2.3.2 Receiver Interrupts
        3. 36.2.3.3 Configuring Interrupts
        4. 36.2.3.4 Handling Interrupts
      4. 36.2.4 RTDMA Interface
      5. 36.2.5 External Frame Trigger Mux
    3. 36.3 FSI Functional Description
      1. 36.3.1 Introduction to Operation
      2. 36.3.2 FSI Transmitter Module
        1. 36.3.2.1 Initialization
        2. 36.3.2.2 FSI_TX Clocking
        3. 36.3.2.3 Transmitting Frames
          1. 36.3.2.3.1 Software Triggered Frames
          2. 36.3.2.3.2 Externally Triggered Frames
          3. 36.3.2.3.3 Ping Frame Generation
            1. 36.3.2.3.3.1 Automatic Ping Frames
            2. 36.3.2.3.3.2 Software Triggered Ping Frame
            3. 36.3.2.3.3.3 Externally Triggered Ping Frame
          4. 36.3.2.3.4 Transmitting Frames with RTDMA
        4. 36.3.2.4 Transmit Buffer Management
        5. 36.3.2.5 CRC Submodule
        6. 36.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 36.3.2.7 Reset
      3. 36.3.3 FSI Receiver Module
        1. 36.3.3.1  Initialization
        2. 36.3.3.2  FSI_RX Clocking
        3. 36.3.3.3  Receiving Frames
          1. 36.3.3.3.1 Receiving Frames with RTDMA
        4. 36.3.3.4  Ping Frame Watchdog
        5. 36.3.3.5  Frame Watchdog
        6. 36.3.3.6  Delay Line Control
        7. 36.3.3.7  Buffer Management
        8. 36.3.3.8  CRC Submodule
        9. 36.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 36.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 36.3.3.11 FSI_RX Reset
      4. 36.3.4 Frame Format
        1. 36.3.4.1 FSI Frame Phases
        2. 36.3.4.2 Frame Types
          1. 36.3.4.2.1 Ping Frames
          2. 36.3.4.2.2 Error Frames
          3. 36.3.4.2.3 Data Frames
        3. 36.3.4.3 Multi-Lane Transmission
      5. 36.3.5 Flush Sequence
      6. 36.3.6 Internal Loopback
      7. 36.3.7 CRC Generation
      8. 36.3.8 ECC Module
      9. 36.3.9 FSI-SPI Compatibility Mode
        1. 36.3.9.1 Available SPI Modes
          1. 36.3.9.1.1 FSITX as SPI Controller, Transmit Only
            1. 36.3.9.1.1.1 Initialization
            2. 36.3.9.1.1.2 Operation
          2. 36.3.9.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 36.3.9.1.2.1 Initialization
            2. 36.3.9.1.2.2 Operation
          3. 36.3.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 36.3.9.1.3.1 Initialization
            2. 36.3.9.1.3.2 Operation
    4. 36.4 FSI Programing Guide
      1. 36.4.1 Establishing the Communication Link
        1. 36.4.1.1 Establishing the Communication Link from the Main Device
        2. 36.4.1.2 Establishing the Communication Link from the Remote Device
      2. 36.4.2 Register Protection
      3. 36.4.3 Emulation Mode
    5. 36.5 Software
      1. 36.5.1 FSI Registers to Driverlib Functions
      2. 36.5.2 FSI Examples
        1. 36.5.2.1 FSI Loopback:CPU Control - SINGLE_CORE
        2. 36.5.2.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 36.6 FSI Registers
      1. 36.6.1 FSI Base Address Table
      2. 36.6.2 FSI_TX_REGS Registers
      3. 36.6.3 FSI_RX_REGS Registers
  39. 37Inter-Integrated Circuit Module (I2C)
    1. 37.1 Introduction
      1. 37.1.1 I2C Related Collateral
      2. 37.1.2 Features
      3. 37.1.3 Features Not Supported
      4. 37.1.4 Functional Overview
      5. 37.1.5 Clock Generation
      6. 37.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 37.1.6.1 Formula for the Controller Clock Period
    2. 37.2 Configuring Device Pins
    3. 37.3 I2C Module Operational Details
      1. 37.3.1  Input and Output Voltage Levels
      2. 37.3.2  Selecting Pullup Resistors
      3. 37.3.3  Data Validity
      4. 37.3.4  Operating Modes
      5. 37.3.5  I2C Module START and STOP Conditions
      6. 37.3.6  Non-repeat Mode versus Repeat Mode
      7. 37.3.7  Serial Data Formats
        1. 37.3.7.1 7-Bit Addressing Format
        2. 37.3.7.2 10-Bit Addressing Format
        3. 37.3.7.3 Free Data Format
        4. 37.3.7.4 Using a Repeated START Condition
      8. 37.3.8  Clock Synchronization
      9. 37.3.9  Clock Stretching
      10. 37.3.10 Arbitration
      11. 37.3.11 Digital Loopback Mode
      12. 37.3.12 NACK Bit Generation
    4. 37.4 Interrupt Requests Generated by the I2C Module
      1. 37.4.1 Basic I2C Interrupt Requests
      2. 37.4.2 I2C FIFO Interrupts
    5. 37.5 Resetting or Disabling the I2C Module
    6. 37.6 Software
      1. 37.6.1 I2C Registers to Driverlib Functions
      2. 37.6.2 I2C Examples
        1. 37.6.2.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 37.6.2.2 I2C EEPROM - SINGLE_CORE
        3. 37.6.2.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 37.6.2.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 37.6.2.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 37.7 I2C Registers
      1. 37.7.1 I2C Base Address Table
      2. 37.7.2 I2C_REGS Registers
  40. 38Power Management Bus Module (PMBus)
    1. 38.1 Introduction
      1. 38.1.1 PMBUS Related Collateral
      2. 38.1.2 Features
      3. 38.1.3 Block Diagram
    2. 38.2 Configuring Device Pins
    3. 38.3 Target Mode Operation
      1. 38.3.1 Configuration
      2. 38.3.2 Message Handling
        1. 38.3.2.1  Quick Command
        2. 38.3.2.2  Send Byte
        3. 38.3.2.3  Receive Byte
        4. 38.3.2.4  Write Byte and Write Word
        5. 38.3.2.5  Read Byte and Read Word
        6. 38.3.2.6  Process Call
        7. 38.3.2.7  Block Write
        8. 38.3.2.8  Block Read
        9. 38.3.2.9  Block Write-Block Read Process Call
        10. 38.3.2.10 Alert Response
        11. 38.3.2.11 Extended Command
        12. 38.3.2.12 Group Command
    4. 38.4 Controller Mode Operation
      1. 38.4.1 Configuration
      2. 38.4.2 Message Handling
        1. 38.4.2.1  Quick Command
        2. 38.4.2.2  Send Byte
        3. 38.4.2.3  Receive Byte
        4. 38.4.2.4  Write Byte and Write Word
        5. 38.4.2.5  Read Byte and Read Word
        6. 38.4.2.6  Process Call
        7. 38.4.2.7  Block Write
        8. 38.4.2.8  Block Read
        9. 38.4.2.9  Block Write-Block Read Process Call
        10. 38.4.2.10 Alert Response
        11. 38.4.2.11 Extended Command
        12. 38.4.2.12 Group Command
    5. 38.5 Software
      1. 38.5.1 PMBUS Registers to Driverlib Functions
    6. 38.6 PMBUS Registers
      1. 38.6.1 PMBUS Base Address Table
      2. 38.6.2 PMBUS_REGS Registers
  41. 39Universal Asynchronous Receiver/Transmitter (UART)
    1. 39.1 Introduction
      1. 39.1.1 Features
      2. 39.1.2 UART Related Collateral
      3. 39.1.3 Block Diagram
    2. 39.2 Functional Description
      1. 39.2.1 Transmit and Receive Logic
      2. 39.2.2 Baud-Rate Generation
      3. 39.2.3 Data Transmission
      4. 39.2.4 Serial IR (SIR)
      5. 39.2.5 9-Bit UART Mode
      6. 39.2.6 FIFO Operation
      7. 39.2.7 Interrupts
      8. 39.2.8 Loopback Operation
      9. 39.2.9 RTDMA Operation
        1. 39.2.9.1 Receiving Data Using UART with RTDMA
        2. 39.2.9.2 Transmitting Data Using UART with RTDMA
    3. 39.3 Initialization and Configuration
    4. 39.4 Software
      1. 39.4.1 UART Registers to Driverlib Functions
      2. 39.4.2 UART Examples
        1. 39.4.2.1 UART Loopback - SINGLE_CORE
        2. 39.4.2.2 UART Loopback with Interrupt - SINGLE_CORE
        3. 39.4.2.3 UART Loopback with DMA - SINGLE_CORE
        4. 39.4.2.4 UART Echoback - SINGLE_CORE
    5. 39.5 UART Registers
      1. 39.5.1 UART Base Address Table
      2. 39.5.2 UART_REGS Registers
      3. 39.5.3 UART_REGS_WRITE Registers
  42. 40Local Interconnect Network (LIN)
    1. 40.1 LIN Overview
      1. 40.1.1 LIN Mode Features
      2. 40.1.2 SCI Mode Features
      3. 40.1.3 Block Diagram
    2. 40.2 Serial Communications Interface Module
      1. 40.2.1 SCI Communication Formats
        1. 40.2.1.1 SCI Frame Formats
        2. 40.2.1.2 SCI Asynchronous Timing Mode
        3. 40.2.1.3 SCI Baud Rate
          1. 40.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 40.2.1.4 SCI Multiprocessor Communication Modes
          1. 40.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 40.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 40.2.1.5 SCI Multibuffered Mode
      2. 40.2.2 SCI Interrupts
        1. 40.2.2.1 Transmit Interrupt
        2. 40.2.2.2 Receive Interrupt
        3. 40.2.2.3 WakeUp Interrupt
        4. 40.2.2.4 Error Interrupts
      3. 40.2.3 SCI RTDMA Interface
        1. 40.2.3.1 Receive RTDMA Requests
        2. 40.2.3.2 Transmit RTDMA Requests
      4. 40.2.4 SCI Configurations
        1. 40.2.4.1 Receiving Data
          1. 40.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 40.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 40.2.4.2 Transmitting Data
          1. 40.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 40.2.5 SCI Low-Power Mode
        1. 40.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 40.3 Local Interconnect Network Module
      1. 40.3.1 LIN Communication Formats
        1. 40.3.1.1  LIN Standards
        2. 40.3.1.2  Message Frame
          1. 40.3.1.2.1 Message Header
          2. 40.3.1.2.2 Response
        3. 40.3.1.3  Synchronizer
        4. 40.3.1.4  Baud Rate
          1. 40.3.1.4.1 Fractional Divider
          2. 40.3.1.4.2 Superfractional Divider
            1. 40.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 40.3.1.5  Header Generation
          1. 40.3.1.5.1 Event Triggered Frame Handling
          2. 40.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 40.3.1.6  Extended Frames Handling
        7. 40.3.1.7  Timeout Control
          1. 40.3.1.7.1 No-Response Error (NRE)
          2. 40.3.1.7.2 Bus Idle Detection
          3. 40.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 40.3.1.8  TXRX Error Detector (TED)
          1. 40.3.1.8.1 Bit Errors
          2. 40.3.1.8.2 Physical Bus Errors
          3. 40.3.1.8.3 ID Parity Errors
          4. 40.3.1.8.4 Checksum Errors
        9. 40.3.1.9  Message Filtering and Validation
        10. 40.3.1.10 Receive Buffers
        11. 40.3.1.11 Transmit Buffers
      2. 40.3.2 LIN Interrupts
      3. 40.3.3 Servicing LIN Interrupts
      4. 40.3.4 LIN RTDMA Interface
        1. 40.3.4.1 LIN Receive RTDMA Requests
        2. 40.3.4.2 LIN Transmit RTDMA Requests
      5. 40.3.5 LIN Configurations
        1. 40.3.5.1 Receiving Data
          1. 40.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 40.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 40.3.5.2 Transmitting Data
          1. 40.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 40.4 Low-Power Mode
      1. 40.4.1 Entering Sleep Mode
      2. 40.4.2 Wakeup
      3. 40.4.3 Wakeup Timeouts
    5. 40.5 Emulation Mode
    6. 40.6 Software
      1. 40.6.1 LIN Registers to Driverlib Functions
      2. 40.6.2 LIN Examples
        1. 40.6.2.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 40.6.2.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 40.6.2.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 40.6.2.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 40.6.2.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 40.7 LIN Registers
      1. 40.7.1 LIN Base Address Table
      2. 40.7.2 LIN_REGS Registers
  43. 41Serial Peripheral Interface (SPI)
    1. 41.1 Introduction
      1. 41.1.1 Features
      2. 41.1.2 Block Diagram
    2. 41.2 System-Level Integration
      1. 41.2.1 SPI Module Signals
      2. 41.2.2 Configuring Device Pins
        1. 41.2.2.1 GPIOs Required for High-Speed Mode
      3. 41.2.3 SPI Interrupts
      4. 41.2.4 RTDMA Support
    3. 41.3 SPI Operation
      1. 41.3.1  Introduction to Operation
      2. 41.3.2  Controller Mode
      3. 41.3.3  Peripheral Mode
      4. 41.3.4  Data Format
        1. 41.3.4.1 Transmission of Bit from SPIRXBUF
      5. 41.3.5  Baud Rate Selection
        1. 41.3.5.1 Baud Rate Determination
        2. 41.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
        3. 41.3.5.3 Baud Rate Calculation
      6. 41.3.6  SPI Clocking Schemes
      7. 41.3.7  SPI FIFO Description
      8. 41.3.8  SPI RTDMA Transfers
        1. 41.3.8.1 Transmitting Data Using SPI with RTDMA
        2. 41.3.8.2 Receiving Data Using SPI with RTDMA
      9. 41.3.9  SPI High-Speed Mode
      10. 41.3.10 SPI 3-Wire Mode Description
    4. 41.4 Programming Procedure
      1. 41.4.1 Initialization Upon Reset
      2. 41.4.2 Configuring the SPI
      3. 41.4.3 Configuring the SPI for High-Speed Mode
      4. 41.4.4 Data Transfer Example
      5. 41.4.5 SPI 3-Wire Mode Code Examples
        1. 41.4.5.1 3-Wire Controller Mode Transmit
        2.       1703
          1. 41.4.5.2.1 3-Wire Controller Mode Receive
        3.       1705
          1. 41.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1707
          1. 41.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 41.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 41.5 Software
      1. 41.5.1 SPI Registers to Driverlib Functions
      2. 41.5.2 SPI Examples
        1. 41.5.2.1 SPI Digital Loopback - SINGLE_CORE
        2. 41.5.2.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 41.5.2.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 41.5.2.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 41.5.2.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 41.6 SPI Registers
      1. 41.6.1 SPI Base Address Table
      2. 41.6.2 SPI_REGS Registers
  44. 42Single Edge Nibble Transmission (SENT)
    1. 42.1 Introduction
      1. 42.1.1 Features
      2. 42.1.2 SENT Related Collateral
    2. 42.2 Advanced Topologies: MTPG
      1. 42.2.1 MTPG Features
      2. 42.2.2 MTPG Description
      3. 42.2.3 Channel Triggers
      4. 42.2.4 Timeout
    3. 42.3 Protocol Description
      1. 42.3.1 Nibble Frame Format
      2. 42.3.2 CRC
      3. 42.3.3 Short Serial Message Format
      4. 42.3.4 Enhanced Serial Message Format
      5. 42.3.5 Enhanced Serial Message Format CRC
      6. 42.3.6 Receive Modes
    4. 42.4 RTDMA Trigger
    5. 42.5 Interrupts Configuration
    6. 42.6 Glitch Filter
    7. 42.7 Software
      1. 42.7.1 SENT Registers to Driverlib Functions
      2. 42.7.2 SENT Examples
        1. 42.7.2.1 SENT Single Sensor - SINGLE_CORE
    8. 42.8 SENT Registers
      1. 42.8.1 SENT Base Address Table
      2. 42.8.2 SENT_CFG Registers
      3. 42.8.3 SENT_MEM Registers
      4. 42.8.4 SENT_MTPG Registers
  45. 43â–º SECURITY PERIPHERALS
    1.     Technical Reference Manual Overview
  46. 44Security Modules
    1. 44.1 Hardware Security Module (HSM)
      1. 44.1.1 HSM Related Collateral
    2. 44.2 Cryptographic Accelerators
  47. 45Revision History

24.16.3 ADC_REGS Registers

Table 24-80 lists the memory-mapped registers for the ADC_REGS registers. All register offset addresses not listed in Table 24-80 should be considered as reserved locations and the register contents should not be modified.

Table 24-80 ADC_REGS Registers
OffsetAcronymRegister NameProtection
0hADCCTL1ADC Control 1 Register
2hADCCTL2ADC Control 2 Register
ChADCBURSTCTLADC Burst Control Register
EhADCINTFLGADC Interrupt Flag Register
10hADCINTFLGCLRADC Interrupt Flag Clear Register
12hADCINTOVFADC Interrupt Overflow Register
14hADCINTOVFCLRADC Interrupt Overflow Clear Register
16hADCINTSEL1N2ADC Interrupt 1 and 2 Selection Register
18hADCINTSEL3N4ADC Interrupt 3 and 4 Selection Register
1AhADCSOCPRICTLADC SOC Priority Control Register
1ChADCINTSOCSEL1ADC Interrupt SOC Selection 1 Register
20hADCINTSOCSEL2ADC Interrupt SOC Selection 2 Register
24hADCSOCFLG1ADC SOC Flag 1 Register
28hADCSOCFRC1ADC SOC Force 1 Register
2ChADCSOCOVF1ADC SOC Overflow 1 Register
30hADCSOCOVFCLR1ADC SOC Overflow Clear 1 Register
34hADCSOC0CTLADC SOC0 Control Register
38hADCSOC1CTLADC SOC1 Control Register
3ChADCSOC2CTLADC SOC2 Control Register
40hADCSOC3CTLADC SOC3 Control Register
44hADCSOC4CTLADC SOC4 Control Register
48hADCSOC5CTLADC SOC5 Control Register
4ChADCSOC6CTLADC SOC6 Control Register
50hADCSOC7CTLADC SOC7 Control Register
54hADCSOC8CTLADC SOC8 Control Register
58hADCSOC9CTLADC SOC9 Control Register
5ChADCSOC10CTLADC SOC10 Control Register
60hADCSOC11CTLADC SOC11 Control Register
64hADCSOC12CTLADC SOC12 Control Register
68hADCSOC13CTLADC SOC13 Control Register
6ChADCSOC14CTLADC SOC14 Control Register
70hADCSOC15CTLADC SOC15 Control Register
74hADCSOC16CTLADC SOC16 Control Register
78hADCSOC17CTLADC SOC17 Control Register
7ChADCSOC18CTLADC SOC18 Control Register
80hADCSOC19CTLADC SOC19 Control Register
84hADCSOC20CTLADC SOC20 Control Register
88hADCSOC21CTLADC SOC21 Control Register
8ChADCSOC22CTLADC SOC22 Control Register
90hADCSOC23CTLADC SOC23 Control Register
94hADCSOC24CTLADC SOC24 Control Register
98hADCSOC25CTLADC SOC25 Control Register
9ChADCSOC26CTLADC SOC26 Control Register
A0hADCSOC27CTLADC SOC27 Control Register
A4hADCSOC28CTLADC SOC28 Control Register
A8hADCSOC29CTLADC SOC29 Control Register
AChADCSOC30CTLADC SOC30 Control Register
B0hADCSOC31CTLADC SOC31 Control Register
B4hADCEVTSTATADC Event Status Register
B8hADCEVTCLRADC Event Clear Register
BChADCEVTSELADC Event Selection Register
C0hADCEVTINTSELADC Event Interrupt Selection Register
C4hADCOSDETECTADC Open and Shorts Detect Register
C6hADCCOUNTERADC Counter Register
C8hADCREVADC Revision Register
CAhADCOFFTRIMADC Offset Trim Register 1
CChADCOFFTRIM2ADC Offset Trim Register 2
CEhADCOFFTRIM3ADC Offset Trim Register 3
D4hADCPPB1CONFIGADC PPB{#} Config Register
D6hADCPPB1STAMPADC PPB1 Sample Delay Time Stamp Register
D8hADCPPB1OFFCALADC PPB1 Offset Calibration Register
DAhADCPPB1OFFREFADC PPB1 Offset Reference Register
DChADCPPB1TRIPHIADC PPB1 Trip High Register
E0hADCPPB1TRIPLOADC PPB1 Trip Low/Trigger Time Stamp Register
E4hADCPPBTRIP1FILCTLADCEVT1 Trip High Filter Control Register
E8hADCPPBTRIP1FILCLKCTLADCEVT1 Trip High Filter Prescale Control Register
F4hADCPPB2CONFIGADC PPB{#} Config Register
F6hADCPPB2STAMPADC PPB2 Sample Delay Time Stamp Register
F8hADCPPB2OFFCALADC PPB2 Offset Calibration Register
FAhADCPPB2OFFREFADC PPB2 Offset Reference Register
FChADCPPB2TRIPHIADC PPB2 Trip High Register
100hADCPPB2TRIPLOADC PPB2 Trip Low/Trigger Time Stamp Register
104hADCPPBTRIP2FILCTLADCEVT2 Trip High Filter Control Register
108hADCPPBTRIP2FILCLKCTLADCEVT2 Trip High Filter Prescale Control Register
114hADCPPB3CONFIGADC PPB{#} Config Register
116hADCPPB3STAMPADC PPB3 Sample Delay Time Stamp Register
118hADCPPB3OFFCALADC PPB3 Offset Calibration Register
11AhADCPPB3OFFREFADC PPB3 Offset Reference Register
11ChADCPPB3TRIPHIADC PPB3 Trip High Register
120hADCPPB3TRIPLOADC PPB3 Trip Low/Trigger Time Stamp Register
124hADCPPBTRIP3FILCTLADCEVT3 Trip High Filter Control Register
128hADCPPBTRIP3FILCLKCTLADCEVT3 Trip High Filter Prescale Control Register
134hADCPPB4CONFIGADC PPB{#} Config Register
136hADCPPB4STAMPADC PPB4 Sample Delay Time Stamp Register
138hADCPPB4OFFCALADC PPB4 Offset Calibration Register
13AhADCPPB4OFFREFADC PPB4 Offset Reference Register
13ChADCPPB4TRIPHIADC PPB4 Trip High Register
140hADCPPB4TRIPLOADC PPB4 Trip Low/Trigger Time Stamp Register
144hADCPPBTRIP4FILCTLADCEVT4 Trip High Filter Control Register
148hADCPPBTRIP4FILCLKCTLADCEVT4 Trip High Filter Prescale Control Register
154hADCSAFECHECKRESENADC Safe Check Result Enable Register
158hADCSAFECHECKRESEN2ADC Safe Check Result Enable 2 Register
172hADCINTCYCLEADC Early Interrupt Generation Cycle
174hADCINLTRIM1ADC Linearity Trim 1 Register
178hADCINLTRIM2ADC Linearity Trim 2 Register
17ChADCINLTRIM3ADC Linearity Trim 3 Register
180hADCINLTRIM4ADC Linearity Trim 4 Register
184hADCINLTRIM5ADC Linearity Trim 5 Register
188hADCINLTRIM6ADC Linearity Trim 6 Register
18EhADCREV2ADC Wrapper Revision Register
194hREP1CTLADC Trigger Repeater 1 Control Register
198hREP1NADC Trigger Repeater 1 N Select Register
19ChREP1PHASEADC Trigger Repeater 1 Phase Select Register
1A0hREP1SPREADADC Trigger Repeater 1 Spread Select Register
1A4hREP1FRCADC Trigger Repeater 1 Software Force Register
1B4hREP2CTLADC Trigger Repeater 2 Control Register
1B8hREP2NADC Trigger Repeater 2 N Select Register
1BChREP2PHASEADC Trigger Repeater 2 Phase Select Register
1C0hREP2SPREADADC Trigger Repeater 2 Spread Select Register
1C4hREP2FRCADC Trigger Repeater 2 Software Force Register
1D4hADCPPB1LIMITADC PPB1Conversion Count Limit Register
1D8hADCPPBP1PCOUNTADC PPB1 Partial Conversion Count Register
1DChADCPPB1CONFIG2ADC PPB1 Sum Shift Register
1E0hADCPPB1PSUMADC PPB1 Partial Sum Register
1E4hADCPPB1PMAXADC PPB1 Partial Max Register
1E8hADCPPB1PMAXIADC PPB1 Partial Max Index Register
1EChADCPPB1PMINADC PPB1 Partial MIN Register
1F0hADCPPB1PMINIADC PPB1 Partial Min Index Register
1F4hADCPPB1TRIPLO2ADC PPB1 Extended Trip Low Register
208hADCPPB2LIMITADC PPB2Conversion Count Limit Register
20ChADCPPBP2PCOUNTADC PPB2 Partial Conversion Count Register
210hADCPPB2CONFIG2ADC PPB2 Sum Shift Register
214hADCPPB2PSUMADC PPB2 Partial Sum Register
218hADCPPB2PMAXADC PPB2 Partial Max Register
21ChADCPPB2PMAXIADC PPB2 Partial Max Index Register
220hADCPPB2PMINADC PPB2 Partial MIN Register
224hADCPPB2PMINIADC PPB2 Partial Min Index Register
228hADCPPB2TRIPLO2ADC PPB2 Extended Trip Low Register
23ChADCPPB3LIMITADC PPB3Conversion Count Limit Register
240hADCPPBP3PCOUNTADC PPB3 Partial Conversion Count Register
244hADCPPB3CONFIG2ADC PPB3 Sum Shift Register
248hADCPPB3PSUMADC PPB3 Partial Sum Register
24ChADCPPB3PMAXADC PPB3 Partial Max Register
250hADCPPB3PMAXIADC PPB3 Partial Max Index Register
254hADCPPB3PMINADC PPB3 Partial MIN Register
258hADCPPB3PMINIADC PPB3 Partial Min Index Register
25ChADCPPB3TRIPLO2ADC PPB3 Extended Trip Low Register
270hADCPPB4LIMITADC PPB4Conversion Count Limit Register
274hADCPPBP4PCOUNTADC PPB4 Partial Conversion Count Register
278hADCPPB4CONFIG2ADC PPB4 Sum Shift Register
27ChADCPPB4PSUMADC PPB4 Partial Sum Register
280hADCPPB4PMAXADC PPB4 Partial Max Register
284hADCPPB4PMAXIADC PPB4 Partial Max Index Register
288hADCPPB4PMINADC PPB4 Partial MIN Register
28ChADCPPB4PMINIADC PPB4 Partial Min Index Register
290hADCPPB4TRIPLO2ADC PPB4 Extended Trip Low Register

Complex bit access types are encoded to fit into small table cells. Table 24-81 shows the codes that are used for access types in this section.

Table 24-81 ADC_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

24.16.3.1 ADCCTL1 Register (Offset = 0h) [Reset = 0000h]

ADCCTL1 is shown in Figure 24-104 and described in Table 24-82.

Return to the Summary Table.

ADC Control 1 Register

Figure 24-104 ADCCTL1 Register
15141312111098
TDMAENEXTMUXPRESELECTENADCBSYADCBSYCHN
R/W-0hR/W-0hR-0hR-0h
76543210
ADCPWDNZRESERVEDINTPULSEPOSRESERVED
R/W-0hR-0hR/W-0hR-0h
Table 24-82 ADCCTL1 Register Field Descriptions
BitFieldTypeResetDescription
15TDMAENR/W0hADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core.

0 DMA is triggered at the same time as the CPU interrupt
1 DMA is always triggered at tDMA regardless or whether the ADC is in early interrupt mode or late interrupt mode

Reset type: SYSRSn

14EXTMUXPRESELECTENR/W0hIf th the ADC SOC sequence is deterministic, the ADCEXTMUX pins can be set earlier: at the end of the S+H window of the previous conversion instead of the beginning of the S+H window of the current conversion. This allows some of the external mux settling time to be pipelined with the previous conversion's conversion time. However, this will not work in the case where high-priority SOCs can arrive asynchronously.

0 ADCEXTMUX pins only change at beginning of S+H window
1 ADCEXTMUX pins are set after the end of S+H window based on pending SOCs

Reset type: SYSRSn

13ADCBSYR0hADC Busy. Set when ADC SOC is generated, cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample.

0 ADC is available to sample next channel
1 ADC is busy and cannot sample another channel

Reset type: SYSRSn

12-8ADCBSYCHNR0hADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated.
When ADCBSY=0: holds the value of the last converted SOC
When ADCBSY=1: reflects the SOC currently being processed
00h SOC0 is currently processing or was last SOC converted
01h SOC1 is currently processing or was last SOC converted
02h SOC2 is currently processing or was last SOC converted
03h SOC3 is currently processing or was last SOC converted
04h SOC4 is currently processing or was last SOC converted
05h SOC5 is currently processing or was last SOC converted
06h SOC6 is currently processing or was last SOC converted
07h SOC7 is currently processing or was last SOC converted
08h SOC8 is currently processing or was last SOC converted
09h SOC9 is currently processing or was last SOC converted
0Ah SOC10 is currently processing or was last SOC converted
0Bh SOC11 is currently processing or was last SOC converted
0Ch SOC12 is currently processing or was last SOC converted
0Dh SOC13 is currently processing or was last SOC converted
0Eh SOC14 is currently processing or was last SOC converted
0Fh SOC15 is currently processing or was last SOC converted
10h SOC16 is currently processing or was last SOC converted
11h SOC17 is currently processing or was last SOC converted
12h SOC18 is currently processing or was last SOC converted
13h SOC19 is currently processing or was last SOC converted
14h SOC20 is currently processing or was last SOC converted
15h SOC21 is currently processing or was last SOC converted
16h SOC22 is currently processing or was last SOC converted
17h SOC23 is currently processing or was last SOC converted
18h SOC24 is currently processing or was last SOC converted
19h SOC25 is currently processing or was last SOC converted
1Ah SOC26 is currently processing or was last SOC converted
1Bh SOC27 is currently processing or was last SOC converted
1Ch SOC28 is currently processing or was last SOC converted
1Dh SOC29 is currently processing or was last SOC converted
1Eh SOC30 is currently processing or was last SOC converted
1Fh SOC31 is currently processing or was last SOC converted

Reset type: SYSRSn

7ADCPWDNZR/W0hADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core.

0 All analog circuitry inside the core is powered down
1 All analog circuitry inside the core is powered up

Reset type: SYSRSn

6-3RESERVEDR0hReserved
2INTPULSEPOSR/W0hADC Interrupt Pulse Position.

0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register.
1 Interrupt pulse generation occurs at the end of the conversion, 1 cycle prior to the ADC result latching into its result register

Reset type: SYSRSn

1-0RESERVEDR0hReserved

24.16.3.2 ADCCTL2 Register (Offset = 2h) [Reset = 0000h]

ADCCTL2 is shown in Figure 24-105 and described in Table 24-83.

Return to the Summary Table.

ADC Control 2 Register

Figure 24-105 ADCCTL2 Register
15141312111098
RESERVEDRESERVEDOFFTRIMMODE
R-0hR-0hR/W-0h
76543210
SIGNALMODERESOLUTIONRESERVEDPRESCALE
R/W-0hR/W-0hR-0hR/W-0h
Table 24-83 ADCCTL2 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0hReserved
12-9RESERVEDR0hReserved
8OFFTRIMMODER/W0hADC offset trim mode.
0 = Offset trim supplied by ADCOFFTRIM.OFFTRIM regardless of resolution or signal mode
1 = Offset trim for each combination of resolution, signalmode, and even or odd is supplied by a different field in ADCOFFTRIM, ADCOFFTRIM2, or ADCOFFTRIM3

Reset type: SYSRSn

7SIGNALMODER/W0hSOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode.
0 Single-ended
1 Differential

Reset type: SYSRSn

6RESOLUTIONR/W0hSOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution.
0 12-bit resolution
1 16-bit resolution

Reset type: SYSRSn

5-4RESERVEDR0hReserved
3-0PRESCALER/W0hADC Clock Prescaler.
0000 ADCCLK = Input Clock / 1.0
0001 Invalid
0010 ADCCLK = Input Clock / 2.0
0011 ADCCLK = Input Clock / 2.5
0100 ADCCLK = Input Clock / 3.0
0101 ADCCLK = Input Clock / 3.5
0110 ADCCLK = Input Clock / 4.0
0111 ADCCLK = Input Clock / 4.5
1000 ADCCLK = Input Clock / 5.0
1001 ADCCLK = Input Clock / 5.5
1010 ADCCLK = Input Clock / 6.0
1011 ADCCLK = Input Clock / 6.5
1100 ADCCLK = Input Clock / 7.0
1101 ADCCLK = Input Clock / 7.5
1110 ADCCLK = Input Clock / 8.0
1111 ADCCLK = Input Clock / 8.5

Reset type: SYSRSn

24.16.3.3 ADCBURSTCTL Register (Offset = Ch) [Reset = 0000h]

ADCBURSTCTL is shown in Figure 24-106 and described in Table 24-84.

Return to the Summary Table.

ADC Burst Control Register

Figure 24-106 ADCBURSTCTL Register
15141312111098
BURSTENRESERVEDBURSTSIZE
R/W-0hR-0hR/W-0h
76543210
RESERVEDBURSTTRIGSEL
R-0hR/W-0h
Table 24-84 ADCBURSTCTL Register Field Descriptions
BitFieldTypeResetDescription
15BURSTENR/W0hSOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation.

0 Burst mode is disabled.
1 Burst mode is enabled.

Reset type: SYSRSn

14-13RESERVEDR0hReserved
12-8BURSTSIZER/W0hSOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer, which is advanced as each SOC is converted.

0h 1 SOC converted
1h 2 SOCs converted
2h 3 SOCs converted
3h 4 SOCs converted
4h 5 SOCs converted
5h 6 SOCs converted
6h 7 SOCs converted
7h 8 SOCs converted
8h 9 SOCs converted
9h 10 SOCs converted
Ah 11 SOCs converted
Bh 12 SOCs converted
Ch 13 SOCs converted
Dh 14 SOCs converted
Eh 15 SOCs converted
Fh 16 SOCs converted
10h 17 SOC converted
11h 18 SOCs converted
12h 19 SOCs converted
13h 20 SOCs converted
14h 21 SOCs converted
15h 22 SOCs converted
16h 23 SOCs converted
17h 24 SOCs converted
18h 25 SOCs converted
19h 26 SOCs converted
1Ah 27 SOCs converted
1Bh 28 SOCs converted
1Ch 29 SOCs converted
1Dh 30 SOCs converted
1Eh 31 SOCs converted
1Fh 32 SOCs converted

Note: If the burst causes SOCs to be set for conversion that were already pending, the corresponding bits in the ADCSOCOVF register will be set.

Reset type: SYSRSn

7RESERVEDR0hReserved
6-0BURSTTRIGSELR/W0hSOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.
00h BURSTTRIG0 - Software only
01h BURSTTRIG1 - CPU1 Timer 0, TINT0n
02h BURSTTRIG2 - CPU1 Timer 1, TINT1n
03h BURSTTRIG3 - CPU1 Timer 2, TINT2n
04h BURSTTRIG4 - GPIO, Input X-Bar INPUT5
05h BURSTTRIG5 - ePWM1, ADCSOCA
06h BURSTTRIG6 - ePWM1, ADCSOCB
07h BURSTTRIG7 - ePWM2, ADCSOCA
08h BURSTTRIG8 - ePWM2, ADCSOCB
09h BURSTTRIG9 - ePWM3, ADCSOCA
0Ah BURSTTRIG10 - ePWM3, ADCSOCB
0Bh BURSTTRIG11 - ePWM4, ADCSOCA
0Ch BURSTTRIG12 - ePWM4, ADCSOCB
0Dh BURSTTRIG13 - ePWM5, ADCSOCA
0Eh BURSTTRIG14 - ePWM5, ADCSOCB
0Fh BURSTTRIG15 - ePWM6, ADCSOCA
10h BURSTTRIG16 - ePWM6, ADCSOCB
11h BURSTTRIG17 - ePWM7, ADCSOCA
12h BURSTTRIG18 - ePWM7, ADCSOCB
13h BURSTTRIG19 - ePWM8, ADCSOCA
14h BURSTTRIG20 - ePWM8, ADCSOCB
15h BURSTTRIG21 - ePWM9, ADCSOCA
16h BURSTTRIG22 - ePWM9, ADCSOCB
17h BURSTTRIG23 - ePWM10, ADCSOCA
18h BURSTTRIG24 - ePWM10, ADCSOCB
19h BURSTTRIG25 - ePWM11, ADCSOCA
1Ah BURSTTRIG26 - ePWM11, ADCSOCB
1Bh BURSTTRIG27 - ePWM12, ADCSOCA
1Ch BURSTTRIG28 - ePWM12, ADCSOCB
1Dh - 1Fh - Reserved
20h BURSTTRIG32 - ePWM13, ADCSOCA
21h BURSTTRIG33 - ePWM13, ADCSOCB
22h BURSTTRIG34 - ePWM14, ADCSOCA
23h BURSTTRIG35 - ePWM14, ADCSOCB
24h BURSTTRIG36 - ePWM15, ADCSOCA
25h BURSTTRIG37 - ePWM15, ADCSOCB
26h BURSTTRIG38 - ePWM16, ADCSOCA
27h BURSTTRIG39 - ePWM16, ADCSOCB
28h BURSTTRIG40 - REP1TRIG
29h BURSTTRIG41 - REP2TRIG
2Ah - 2Fh - Reserved
30h BURSTTRIG48 - ePWM17, ADCSOCA
31h BURSTTRIG49 - ePWM17, ADCSOCB
32h BURSTTRIG50 - ePWM18, ADCSOCA
33h BURSTTRIG51 - ePWM18, ADCSOCB
34h BURSTTRIG52 - ePWM19, ADCSOCA
35h BURSTTRIG53 - ePWM19, ADCSOCB
36h BURSTTRIG54 - ePWM20, ADCSOCA
37h BURSTTRIG55 - ePWM20, ADCSOCB
38h BURSTTRIG56 - ePWM21, ADCSOCA
39h BURSTTRIG57 - ePWM21, ADCSOCB
3Ah BURSTTRIG58 - ePWM22, ADCSOCA
3Bh BURSTTRIG59 - ePWM22, ADCSOCB
3Ch BURSTTRIG60 - ePWM23, ADCSOCA
3Dh BURSTTRIG61 - ePWM23, ADCSOCB
3Eh BURSTTRIG62 - ePWM24, ADCSOCA
3Fh BURSTTRIG63 - ePWM24, ADCSOCB
40h BURSTTRIG64 - ePWM25, ADCSOCA
41h BURSTTRIG65 - ePWM25, ADCSOCB
42h BURSTTRIG66 - ePWM26, ADCSOCA
43h BURSTTRIG67 - ePWM26, ADCSOCB
44h BURSTTRIG68 - ePWM27, ADCSOCA
45h BURSTTRIG69 - ePWM27, ADCSOCB
46h BURSTTRIG70 - ePWM28, ADCSOCA
47h BURSTTRIG71 - ePWM28, ADCSOCB
48h BURSTTRIG72 - ePWM29, ADCSOCA
49h BURSTTRIG73 - ePWM29, ADCSOCB
4Ah BURSTTRIG74 - ePWM30, ADCSOCA
4Bh BURSTTRIG75 - ePWM30, ADCSOCB
4Ch BURSTTRIG76 - ePWM31, ADCSOCA
4Dh BURSTTRIG77 - ePWM31, ADCSOCB
4Eh BURSTTRIG78 - ePWM32, ADCSOCA
4Fh BURSTTRIG79 - ePWM32, ADCSOCB
50h BURSTTRIG80 eCAP1
51h BURSTTRIG81 eCAP2
52h BURSTTRIG82 eCAP3
53h BURSTTRIG83 eCAP4
54h BURSTTRIG84 eCAP5
55h BURSTTRIG85 eCAP6
56h BURSTTRIG86 eCAP7
57h BURSTTRIG87 eCAP8
58h - 7Fh - Reserved

Reset type: SYSRSn

24.16.3.4 ADCINTFLG Register (Offset = Eh) [Reset = 0000h]

ADCINTFLG is shown in Figure 24-107 and described in Table 24-85.

Return to the Summary Table.

ADC Interrupt Flag Register

Figure 24-107 ADCINTFLG Register
15141312111098
RESERVED
R-0h
76543210
ADCINT4RESULTADCINT3RESULTADCINT2RESULTADCINT1RESULTADCINT4ADCINT3ADCINT2ADCINT1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 24-85 ADCINTFLG Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0hReserved
7ADCINT4RESULTR0hADC Interrupt 4 Results Ready Flag. This flag is set when the conversions results associated with ADCINT4 latch into the corresponding results register.

0 Conversion results have not latched
1 Conversion results have latched

This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register.

This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT4 flag.

In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE.

In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch.

Reset type: SYSRSn

6ADCINT3RESULTR0hADC Interrupt 3 Results Ready Flag. This flag is set when the conversions results associated with ADCINT3 latch into the corresponding results register.

0 Conversion results have not latched
1 Conversion results have latched

This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register.

This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT3 flag.

In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE.

In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch.

Reset type: SYSRSn

5ADCINT2RESULTR0hADC Interrupt 2 Results Ready Flag. This flag is set when the conversions results associated with ADCINT2 latch into the corresponding results register.

0 Conversion results have not latched
1 Conversion results have latched

This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register.

This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT2 flag.

In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE.

In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch.

Reset type: SYSRSn

4ADCINT1RESULTR0hADC Interrupt 1 Results Ready Flag. This flag is set when the conversions results associated with ADCINT1 latch into the corresponding results register.

0 Conversion results have not latched
1 Conversion results have latched

This flag can be used in an ISR that is entered in early interrupt mode to ensure that the corresponding results are ready before proceeding to read the result register.

This flag can be cleared via the ACK bit in the ADCINTFLGCLR that also clears the ADCINT1 flag.

In case results latch and this flag is already set, the corresponding flag in ADCINTOVF is NOT set. This flag does NOT have to be cleared in order for ADCINT ISRs to propagate to the PIE.

In case the associated SOC is associated with a PPB or PPBs, the flag will not be set until all associated PPB results latch.

Reset type: SYSRSn

3ADCINT4R0hADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear.

0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated

If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register.

Reset type: SYSRSn

2ADCINT3R0hADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear.

0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated

If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register.

Reset type: SYSRSn

1ADCINT2R0hADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear.

0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated

If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register.

Reset type: SYSRSn

0ADCINT1R0hADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear.

0 No ADC interrupt pulse generated
1 ADC interrupt pulse generated

If the ADC interrupt is placed in continue to interrupt mode (INTSELxNy register) then further interrupt pulses are generated whenever a selected EOC event occurs even if the flag bit is set. If the continuous mode is not enabled, then no further interrupt pulses are generated until the user clears this flag bit using the ADCINTFLGCLR register. Rather, an ADC interrupt overflow event occurs in the ADCINTOVF register.

Reset type: SYSRSn

24.16.3.5 ADCINTFLGCLR Register (Offset = 10h) [Reset = 0000h]

ADCINTFLGCLR is shown in Figure 24-108 and described in Table 24-86.

Return to the Summary Table.

ADC Interrupt Flag Clear Register

Figure 24-108 ADCINTFLGCLR Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDADCINT4ADCINT3ADCINT2ADCINT1
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 24-86 ADCINTFLGCLR Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0hReserved
3ADCINT4R-0/W1C0hADC Interrupt 4 Flag Clear. Reads return 0.

0 No action
1 Clears ADCINT4 and ADCINT4RESULT flags in the ADCINTFLG register.
If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

2ADCINT3R-0/W1C0hADC Interrupt 3 Flag Clear. Reads return 0.

0 No action
1 Clears ADCINT3 and ADCINT3RESULT flags in the ADCINTFLG register.
If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

1ADCINT2R-0/W1C0hADC Interrupt 2 Flag Clear. Reads return 0.

0 No action
1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG register. . If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

0ADCINT1R-0/W1C0hADC Interrupt 1 Flag Clear. Reads return 0.

0 No action
1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG register.
If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

24.16.3.6 ADCINTOVF Register (Offset = 12h) [Reset = 0000h]

ADCINTOVF is shown in Figure 24-109 and described in Table 24-87.

Return to the Summary Table.

ADC Interrupt Overflow Register

Figure 24-109 ADCINTOVF Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDADCINT4ADCINT3ADCINT2ADCINT1
R-0hR-0hR-0hR-0hR-0h
Table 24-87 ADCINTOVF Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0hReserved
3ADCINT4R0hADC Interrupt 4 Overflow Flags

Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs.

0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.

The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.

Reset type: SYSRSn

2ADCINT3R0hADC Interrupt 3 Overflow Flags

Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs.

0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.

The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.

Reset type: SYSRSn

1ADCINT2R0hADC Interrupt 2 Overflow Flags

Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs.

0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.

The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.

Reset type: SYSRSn

0ADCINT1R0hADC Interrupt 1 Overflow Flags

Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs.

0 No ADC interrupt overflow event detected.
1 ADC Interrupt overflow event detected.

The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.

Reset type: SYSRSn

24.16.3.7 ADCINTOVFCLR Register (Offset = 14h) [Reset = 0000h]

ADCINTOVFCLR is shown in Figure 24-110 and described in Table 24-88.

Return to the Summary Table.

ADC Interrupt Overflow Clear Register

Figure 24-110 ADCINTOVFCLR Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDADCINT4ADCINT3ADCINT2ADCINT1
R-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0hR-0/W1C-0h
Table 24-88 ADCINTOVFCLR Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR0hReserved
3ADCINT4R-0/W1C0hADC Interrupt 4 Overflow Clear Bits

0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.

Reset type: SYSRSn

2ADCINT3R-0/W1C0hADC Interrupt 3 Overflow Clear Bits

0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.

Reset type: SYSRSn

1ADCINT2R-0/W1C0hADC Interrupt 2 Overflow Clear Bits

0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.

Reset type: SYSRSn

0ADCINT1R-0/W1C0hADC Interrupt 1 Overflow Clear Bits

0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.

Reset type: SYSRSn

24.16.3.8 ADCINTSEL1N2 Register (Offset = 16h) [Reset = 0000h]

ADCINTSEL1N2 is shown in Figure 24-111 and described in Table 24-89.

Return to the Summary Table.

ADC Interrupt 1 and 2 Selection Register

Figure 24-111 ADCINTSEL1N2 Register
15141312111098
INT2EINT2CONTINT2SEL
R/W-0hR/W-0hR/W-0h
76543210
INT1EINT1CONTINT1SEL
R/W-0hR/W-0hR/W-0h
Table 24-89 ADCINTSEL1N2 Register Field Descriptions
BitFieldTypeResetDescription
15INT2ER/W0hADCINT2 Interrupt Enable
0 ADCINT2 is disabled
1 ADCINT2 is enabled

Reset type: SYSRSn

14INT2CONTR/W0hADCINT2 Continue to Interrupt Mode
0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user.
1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not.

Reset type: SYSRSn

13-8INT2SELR/W0hADCINT2 EOC Source Select
00h EOC0 is trigger for ADCINT2
01h EOC1 is trigger for ADCINT2
02h EOC2 is trigger for ADCINT2
03h EOC3 is trigger for ADCINT2
04h EOC4 is trigger for ADCINT2
05h EOC5 is trigger for ADCINT2
06h EOC6 is trigger for ADCINT2
07h EOC7 is trigger for ADCINT2
08h EOC8 is trigger for ADCINT2
09h EOC9 is trigger for ADCINT2
0Ah EOC10 is trigger for ADCINT2
0Bh EOC11 is trigger for ADCINT2
0Ch EOC12 is trigger for ADCINT2
0Dh EOC13 is trigger for ADCINT2
0Eh EOC14 is trigger for ADCINT2
0Fh EOC15 is trigger for ADCINT2
10h EOC16 is trigger for ADCINT2
11h EOC17 is trigger for ADCINT2
12h EOC18 is trigger for ADCINT2
13h EOC19 is trigger for ADCINT2
14h EOC20 is trigger for ADCINT2
15h EOC21 is trigger for ADCINT2
16h EOC22 is trigger for ADCINT2
17h EOC23 is trigger for ADCINT2
18h EOC24 is trigger for ADCINT2
19h EOC25 is trigger for ADCINT2
1Ah EOC26 is trigger for ADCINT2
1Bh EOC27 is trigger for ADCINT2
1Ch EOC28 is trigger for ADCINT2
1Dh EOC29 is trigger for ADCINT2
1Eh EOC30 is trigger for ADCINT2
1Fh EOC31 is trigger for ADCINT2
20h OSINT1 is trigger for ADCINT2
21h OSINT2 is trigger for ADCINT2
22h OSINT3 is trigger for ADCINT2
23h OSINT4 is trigger for ADCINT2

Reset type: SYSRSn

7INT1ER/W0hADCINT1 Interrupt Enable
0 ADCINT1 is disabled
1 ADCINT1 is enabled

Reset type: SYSRSn

6INT1CONTR/W0hADCINT1 Continue to Interrupt Mode
0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user.
1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not.

Reset type: SYSRSn

5-0INT1SELR/W0hADCINT1 EOC Source Select
00h EOC0 is trigger for ADCINT1
01h EOC1 is trigger for ADCINT1
02h EOC2 is trigger for ADCINT1
03h EOC3 is trigger for ADCINT1
04h EOC4 is trigger for ADCINT1
05h EOC5 is trigger for ADCINT1
06h EOC6 is trigger for ADCINT1
07h EOC7 is trigger for ADCINT1
08h EOC8 is trigger for ADCINT1
09h EOC9 is trigger for ADCINT1
0Ah EOC10 is trigger for ADCINT1
0Bh EOC11 is trigger for ADCINT1
0Ch EOC12 is trigger for ADCINT1
0Dh EOC13 is trigger for ADCINT1
0Eh EOC14 is trigger for ADCINT1
0Fh EOC15 is trigger for ADCINT1
10h EOC16 is trigger for ADCINT1
11h EOC17 is trigger for ADCINT1
12h EOC18 is trigger for ADCINT1
13h EOC19 is trigger for ADCINT1
14h EOC20 is trigger for ADCINT1
15h EOC21 is trigger for ADCINT1
16h EOC22 is trigger for ADCINT1
17h EOC23 is trigger for ADCINT1
18h EOC24 is trigger for ADCINT1
19h EOC25 is trigger for ADCINT1
1Ah EOC26 is trigger for ADCINT1
1Bh EOC27 is trigger for ADCINT1
1Ch EOC28 is trigger for ADCINT1
1Dh EOC29 is trigger for ADCINT1
1Eh EOC30 is trigger for ADCINT1
1Fh EOC31 is trigger for ADCINT1
20h OSINT1 is trigger for ADCINT1
21h OSINT2 is trigger for ADCINT1
22h OSINT3 is trigger for ADCINT1
23h OSINT4 is trigger for ADCINT1

Reset type: SYSRSn

24.16.3.9 ADCINTSEL3N4 Register (Offset = 18h) [Reset = 0000h]

ADCINTSEL3N4 is shown in Figure 24-112 and described in Table 24-90.

Return to the Summary Table.

ADC Interrupt 3 and 4 Selection Register

Figure 24-112 ADCINTSEL3N4 Register
15141312111098
INT4EINT4CONTINT4SEL
R/W-0hR/W-0hR/W-0h
76543210
INT3EINT3CONTINT3SEL
R/W-0hR/W-0hR/W-0h
Table 24-90 ADCINTSEL3N4 Register Field Descriptions
BitFieldTypeResetDescription
15INT4ER/W0hADCINT4 Interrupt Enable
0 ADCINT4 is disabled
1 ADCINT4 is enabled

Reset type: SYSRSn

14INT4CONTR/W0hADCINT4 Continue to Interrupt Mode
0 No further ADCINT4 pulses are generated until ADCINT4 flag (in ADCINTFLG register) is cleared by user.
1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not.

Reset type: SYSRSn

13-8INT4SELR/W0hADCINT4 EOC Source Select
00h EOC0 is trigger for ADCINT4
01h EOC1 is trigger for ADCINT4
02h EOC2 is trigger for ADCINT4
03h EOC3 is trigger for ADCINT4
04h EOC4 is trigger for ADCINT4
05h EOC5 is trigger for ADCINT4
06h EOC6 is trigger for ADCINT4
07h EOC7 is trigger for ADCINT4
08h EOC8 is trigger for ADCINT4
09h EOC9 is trigger for ADCINT4
0Ah EOC10 is trigger for ADCINT4
0Bh EOC11 is trigger for ADCINT4
0Ch EOC12 is trigger for ADCINT4
0Dh EOC13 is trigger for ADCINT4
0Eh EOC14 is trigger for ADCINT4
0Fh EOC15 is trigger for ADCINT4
10h EOC16 is trigger for ADCINT4
11h EOC17 is trigger for ADCINT4
12h EOC18 is trigger for ADCINT4
13h EOC19 is trigger for ADCINT4
14h EOC20 is trigger for ADCINT4
15h EOC21 is trigger for ADCINT4
16h EOC22 is trigger for ADCINT4
17h EOC23 is trigger for ADCINT4
18h EOC24 is trigger for ADCINT4
19h EOC25 is trigger for ADCINT4
1Ah EOC26 is trigger for ADCINT4
1Bh EOC27 is trigger for ADCINT4
1Ch EOC28 is trigger for ADCINT4
1Dh EOC29 is trigger for ADCINT4
1Eh EOC30 is trigger for ADCINT4
1Fh EOC31 is trigger for ADCINT4
20h OSINT1 is trigger for ADCINT4
21h OSINT2 is trigger for ADCINT4
22h OSINT3 is trigger for ADCINT4
23h OSINT4 is trigger for ADCINT4

Reset type: SYSRSn

7INT3ER/W0hADCINT3 Interrupt Enable
0 ADCINT3 is disabled
1 ADCINT3 is enabled

Reset type: SYSRSn

6INT3CONTR/W0hADCINT3 Continue to Interrupt Mode
0 No further ADCINT3 pulses are generated until ADCINT3 flag (in ADCINTFLG register) is cleared by user.
1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag bit is cleared or not.

Reset type: SYSRSn

5-0INT3SELR/W0hADCINT3 EOC Source Select
00h EOC0 is trigger for ADCINT3
01h EOC1 is trigger for ADCINT3
02h EOC2 is trigger for ADCINT3
03h EOC3 is trigger for ADCINT3
04h EOC4 is trigger for ADCINT3
05h EOC5 is trigger for ADCINT3
06h EOC6 is trigger for ADCINT3
07h EOC7 is trigger for ADCINT3
08h EOC8 is trigger for ADCINT3
09h EOC9 is trigger for ADCINT3
0Ah EOC10 is trigger for ADCINT3
0Bh EOC11 is trigger for ADCINT3
0Ch EOC12 is trigger for ADCINT3
0Dh EOC13 is trigger for ADCINT3
0Eh EOC14 is trigger for ADCINT3
0Fh EOC15 is trigger for ADCINT3
10h EOC16 is trigger for ADCINT3
11h EOC17 is trigger for ADCINT3
12h EOC18 is trigger for ADCINT3
13h EOC19 is trigger for ADCINT3
14h EOC20 is trigger for ADCINT3
15h EOC21 is trigger for ADCINT3
16h EOC22 is trigger for ADCINT3
17h EOC23 is trigger for ADCINT3
18h EOC24 is trigger for ADCINT3
19h EOC25 is trigger for ADCINT3
1Ah EOC26 is trigger for ADCINT3
1Bh EOC27 is trigger for ADCINT3
1Ch EOC28 is trigger for ADCINT3
1Dh EOC29 is trigger for ADCINT3
1Eh EOC30 is trigger for ADCINT3
1Fh EOC31 is trigger for ADCINT3
20h OSINT1 is trigger for ADCINT3
21h OSINT2 is trigger for ADCINT3
22h OSINT3 is trigger for ADCINT3
23h OSINT4 is trigger for ADCINT3

Reset type: SYSRSn

24.16.3.10 ADCSOCPRICTL Register (Offset = 1Ah) [Reset = 0800h]

ADCSOCPRICTL is shown in Figure 24-113 and described in Table 24-91.

Return to the Summary Table.

ADC SOC Priority Control Register

Figure 24-113 ADCSOCPRICTL Register
15141312111098
RESERVEDRRPOINTER
R-0hR-20h
76543210
RRPOINTERSOCPRIORITY
R-20hR/W-0h
Table 24-91 ADCSOCPRICTL Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0hReserved
11-6RRPOINTERR20hRound Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions.
00h SOC0 was last round robin SOC to convert, SOC1 is highest round robin priority.
01h SOC1 was last round robin SOC to convert, SOC2 is highest round robin priority.
02h SOC2 was last round robin SOC to convert, SOC3 is highest round robin priority.
03h SOC3 was last round robin SOC to convert, SOC4 is highest round robin priority.
04h SOC4 was last round robin SOC to convert, SOC5 is highest round robin priority.
05h SOC5 was last round robin SOC to convert, SOC6 is highest round robin priority.
06h SOC6 was last round robin SOC to convert, SOC7 is highest round robin priority.
07h SOC7 was last round robin SOC to convert, SOC8 is highest round robin priority.
08h SOC8 was last round robin SOC to convert, SOC9 is highest round robin priority.
09h SOC9 was last round robin SOC to convert, SOC10 is highest round robin priority.
0Ah SOC10 was last round robin SOC to convert, SOC11 is highest round robin priority.
0Bh SOC11 was last round robin SOC to convert, SOC12 is highest round robin priority.
0Ch SOC12 was last round robin SOC to convert, SOC13 is highest round robin priority.
0Dh SOC13 was last round robin SOC to convert, SOC14 is highest round robin priority.
0Eh SOC14 was last round robin SOC to convert, SOC15 is highest round robin priority.
0Fh SOC15 was last round robin SOC to convert, SOC16 is highest round robin priority.
10h SOC16 was last round robin SOC to convert, SOC17 is highest round robin priority.
11h SOC17 was last round robin SOC to convert, SOC18 is highest round robin priority.
12h SOC18 was last round robin SOC to convert, SOC19 is highest round robin priority.
13h SOC19 was last round robin SOC to convert, SOC20 is highest round robin priority.
14h SOC20 was last round robin SOC to convert, SOC21 is highest round robin priority.
15h SOC21 was last round robin SOC to convert, SOC22 is highest round robin priority.
16h SOC22 was last round robin SOC to convert, SOC23 is highest round robin priority.
17h SOC23 was last round robin SOC to convert, SOC24 is highest round robin priority.
18h SOC24 was last round robin SOC to convert, SOC25 is highest round robin priority.
19h SOC25 was last round robin SOC to convert, SOC26 is highest round robin priority.
1Ah SOC26 was last round robin SOC to convert, SOC27 is highest round robin priority.
1Bh SOC27 was last round robin SOC to convert, SOC28 is highest round robin priority.
1Ch SOC28 was last round robin SOC to convert, SOC29 is highest round robin priority.
1Dh SOC29 was last round robin SOC to convert, SOC30 is highest round robin priority.
1Eh SOC30 was last round robin SOC to convert, SOC31 is highest round robin priority.
1Fh SOC31 was last round robin SOC to convert, SOC0 is highest round robin priority.
20h Reset value to indicate no SOC has been converted. SOC0 is highest round robin priority. Set to this value when the ADC module is reset by SOFTPRES or when the ADCSOCPRICTL register is written. In the latter case, if a conversion is currently in progress, it will complete and then the new priority will take effect.
Others Invalid value.

Reset type: SYSRSn

5-0SOCPRIORITYR/W0hSOC Priority
Determines the cutoff point for priority mode and round robin arbitration for SOCx
00h SOC priority is handled in round robin mode for all channels.
01h SOC0 is high priority, rest of channels are in round robin mode.
02h SOC0-SOC1 are high priority, SOC2 and greater are in round robin mode.
03h SOC0-SOC2 are high priority, SOC3 and greater are in round robin mode.
04h SOC0-SOC3 are high priority, SOC4 and greater are in round robin mode.
05h SOC0-SOC4 are high priority, SOC5 and greater are in round robin mode.
06h SOC0-SOC5 are high priority, SOC6 and greater are in round robin mode.
07h SOC0-SOC6 are high priority, SOC7 and greater are in round robin mode.
08h SOC0-SOC7 are high priority, SOC8 and greater are in round robin mode.
09h SOC0-SOC8 are high priority, SOC9 and greater are in round robin mode.
0Ah SOC0-SOC9 are high priority, SOC10 and greater are in round robin mode.
0Bh SOC0-SOC10 are high priority, SOC11 and greater are in round robin mode.
0Ch SOC0-SOC11 are high priority, SOC12 and greater are in round robin mode.
0Dh SOC0-SOC12 are high priority, SOC13 and greater are in round robin mode.
0Eh SOC0-SOC13 are high priority, SOC14 and greater are in round robin mode.
0Fh SOC0-SOC14 are high priority, SOC15 and greater are in round robin mode.
10h SOC0-SOC15 are high priority, SOC16 and greater are in round robin mode.
11h SOC0-SOC16 are high priority, SOC17 and greater are in round robin mode.
12h SOC0-SOC17 are high priority, SOC18 and greater are in round robin mode.
13h SOC0-SOC18 are high priority, SOC19 and greater are in round robin mode.
14h SOC0-SOC19 are high priority, SOC20 and greater are in round robin mode.
15h SOC0-SOC20 are high priority, SOC21 and greater are in round robin mode.
16h SOC0-SOC21 are high priority, SOC22 and greater are in round robin mode.
17h SOC0-SOC22 are high priority, SOC23 and greater are in round robin mode.
18h SOC0-SOC23 are high priority, SOC24 and greater are in round robin mode.
19h SOC0-SOC24 are high priority, SOC25 and greater are in round robin mode.
1Ah SOC0-SOC25 are high priority, SOC26 and greater are in round robin mode.
1Bh SOC0-SOC26 are high priority, SOC27 and greater are in round robin mode.
1Ch SOC0-SOC27 are high priority, SOC28 and greater are in round robin mode.
1Dh SOC0-SOC28 are high priority, SOC29 and greater are in round robin mode.
1Eh SOC0-SOC29 are high priority, SOC30 and greater are in round robin mode.
1Fh SOC0-SOC30 are high priority, SOC31 is in round robin mode.
20h All SOCs are in high priority mode, arbitrated by SOC number.
Others Invalid selection.

Reset type: SYSRSn

24.16.3.11 ADCINTSOCSEL1 Register (Offset = 1Ch) [Reset = 00000000h]

ADCINTSOCSEL1 is shown in Figure 24-114 and described in Table 24-92.

Return to the Summary Table.

ADC Interrupt SOC Selection 1 Register

Figure 24-114 ADCINTSOCSEL1 Register
31302928272625242322212019181716
SOC15SOC14SOC13SOC12SOC11SOC10SOC9SOC8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
SOC7SOC6SOC5SOC4SOC3SOC2SOC1SOC0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 24-92 ADCINTSOCSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-30SOC15R/W0hSOC15 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC15. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC15.
10 ADCINT2 will trigger SOC15.
11 Invalid selection.

Reset type: SYSRSn

29-28SOC14R/W0hSOC14 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC14. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC14.
10 ADCINT2 will trigger SOC14.
11 Invalid selection.

Reset type: SYSRSn

27-26SOC13R/W0hSOC13 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC13. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC13.
10 ADCINT2 will trigger SOC13.
11 Invalid selection.

Reset type: SYSRSn

25-24SOC12R/W0hSOC12 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC12. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC12.
10 ADCINT2 will trigger SOC12.
11 Invalid selection.

Reset type: SYSRSn

23-22SOC11R/W0hSOC11 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC11. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC11.
10 ADCINT2 will trigger SOC11.
11 Invalid selection.

Reset type: SYSRSn

21-20SOC10R/W0hSOC10 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC10. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC10.
10 ADCINT2 will trigger SOC10.
11 Invalid selection.

Reset type: SYSRSn

19-18SOC9R/W0hSOC9 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC9.
10 ADCINT2 will trigger SOC9.
11 Invalid selection.

Reset type: SYSRSn

17-16SOC8R/W0hSOC8 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC8.
10 ADCINT2 will trigger SOC8.
11 Invalid selection.

Reset type: SYSRSn

15-14SOC7R/W0hSOC7 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC7.
10 ADCINT2 will trigger SOC7.
11 Invalid selection.

Reset type: SYSRSn

13-12SOC6R/W0hSOC6 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC6.
10 ADCINT2 will trigger SOC6.
11 Invalid selection.

Reset type: SYSRSn

11-10SOC5R/W0hSOC5 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC5.
10 ADCINT2 will trigger SOC5.
11 Invalid selection.

Reset type: SYSRSn

9-8SOC4R/W0hSOC4 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC4.
10 ADCINT2 will trigger SOC4.
11 Invalid selection.

Reset type: SYSRSn

7-6SOC3R/W0hSOC3 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC3.
10 ADCINT2 will trigger SOC3.
11 Invalid selection.

Reset type: SYSRSn

5-4SOC2R/W0hSOC2 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC2.
10 ADCINT2 will trigger SOC2.
11 Invalid selection.

Reset type: SYSRSn

3-2SOC1R/W0hSOC1 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC1.
10 ADCINT2 will trigger SOC1.
11 Invalid selection.

Reset type: SYSRSn

1-0SOC0R/W0hSOC0 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC0.
10 ADCINT2 will trigger SOC0.
11 Invalid selection.

Reset type: SYSRSn

24.16.3.12 ADCINTSOCSEL2 Register (Offset = 20h) [Reset = 00000000h]

ADCINTSOCSEL2 is shown in Figure 24-115 and described in Table 24-93.

Return to the Summary Table.

ADC Interrupt SOC Selection 2 Register

Figure 24-115 ADCINTSOCSEL2 Register
31302928272625242322212019181716
SOC31SOC30SOC29SOC28SOC27SOC26SOC25SOC24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
SOC23SOC22SOC21SOC20SOC19SOC18SOC17SOC16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 24-93 ADCINTSOCSEL2 Register Field Descriptions
BitFieldTypeResetDescription
31-30SOC31R/W0hSOC31 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC31. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC31. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC31.
10 ADCINT2 will trigger SOC31.
11 Invalid selection.

Reset type: SYSRSn

29-28SOC30R/W0hSOC30 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC30. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC30. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC30.
10 ADCINT2 will trigger SOC30.
11 Invalid selection.

Reset type: SYSRSn

27-26SOC29R/W0hSOC29 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC29. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC29. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC29.
10 ADCINT2 will trigger SOC29.
11 Invalid selection.

Reset type: SYSRSn

25-24SOC28R/W0hSOC28 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC28. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC28. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC28.
10 ADCINT2 will trigger SOC28.
11 Invalid selection.

Reset type: SYSRSn

23-22SOC27R/W0hSOC27 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC27. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC27. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC27.
10 ADCINT2 will trigger SOC27.
11 Invalid selection.

Reset type: SYSRSn

21-20SOC26R/W0hSOC26 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC26. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC26. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC26.
10 ADCINT2 will trigger SOC26.
11 Invalid selection.

Reset type: SYSRSn

19-18SOC25R/W0hSOC25 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC25. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC25. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC25.
10 ADCINT2 will trigger SOC25.
11 Invalid selection.

Reset type: SYSRSn

17-16SOC24R/W0hSOC24 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC24. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC24. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC24.
10 ADCINT2 will trigger SOC24.
11 Invalid selection.

Reset type: SYSRSn

15-14SOC23R/W0hSOC23 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC23. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC23. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC23.
10 ADCINT2 will trigger SOC23.
11 Invalid selection.

Reset type: SYSRSn

13-12SOC22R/W0hSOC22 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC22. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC22. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC22.
10 ADCINT2 will trigger SOC22.
11 Invalid selection.

Reset type: SYSRSn

11-10SOC21R/W0hSOC21 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC21. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC21. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC21.
10 ADCINT2 will trigger SOC21.
11 Invalid selection.

Reset type: SYSRSn

9-8SOC20R/W0hSOC20 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC20. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC20. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC20.
10 ADCINT2 will trigger SOC20.
11 Invalid selection.

Reset type: SYSRSn

7-6SOC19R/W0hSOC19 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC19. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC19. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC19.
10 ADCINT2 will trigger SOC19.
11 Invalid selection.

Reset type: SYSRSn

5-4SOC18R/W0hSOC18 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC18. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC18. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC18.
10 ADCINT2 will trigger SOC18.
11 Invalid selection.

Reset type: SYSRSn

3-2SOC17R/W0hSOC17 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC17. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC17. TRIGSEL field alone determines SOC0 trigger.
01 ADCINT1 will trigger SOC17.
10 ADCINT2 will trigger SOC17.
11 Invalid selection.

Reset type: SYSRSn

1-0SOC16R/W0hSOC16 ADC Interrupt Trigger Select. Selects which, if any, ADCINT triggers SOC16. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register.
00 No ADCINT will trigger SOC16. TRIGSEL field alone determines SOC16 trigger.
01 ADCINT1 will trigger SOC16.
10 ADCINT2 will trigger SOC16.
11 Invalid selection.

Reset type: SYSRSn

24.16.3.13 ADCSOCFLG1 Register (Offset = 24h) [Reset = 00000000h]

ADCSOCFLG1 is shown in Figure 24-116 and described in Table 24-94.

Return to the Summary Table.

ADC SOC Flag 1 Register

Figure 24-116 ADCSOCFLG1 Register
3130292827262524
SOC31SOC30SOC29SOC28SOC27SOC26SOC25SOC24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
SOC23SOC22SOC21SOC20SOC19SOC18SOC17SOC16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
SOC15SOC14SOC13SOC12SOC11SOC10SOC9SOC8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
SOC7SOC6SOC5SOC4SOC3SOC2SOC1SOC0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 24-94 ADCSOCFLG1 Register Field Descriptions
BitFieldTypeResetDescription
31SOC31R0hSOC31 Start of Conversion Flag. Indicates the state of SOC31 conversions.

0 No sample pending for SOC15.
1 Trigger has been received and sample is pending for SOC15.

This bit will be automatically cleared when the SOC15 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

30SOC30R0hSOC30 Start of Conversion Flag. Indicates the state of SOC30 conversions.

0 No sample pending for SOC14.
1 Trigger has been received and sample is pending for SOC14.

This bit will be automatically cleared when the SOC14 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

29SOC29R0hSOC29 Start of Conversion Flag. Indicates the state of SOC29 conversions.

0 No sample pending for SOC13.
1 Trigger has been received and sample is pending for SOC13.

This bit will be automatically cleared when the SOC13 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

28SOC28R0hSOC28 Start of Conversion Flag. Indicates the state of SOC28 conversions.

0 No sample pending for SOC12.
1 Trigger has been received and sample is pending for SOC12.

This bit will be automatically cleared when the SOC12 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

27SOC27R0hSOC27 Start of Conversion Flag. Indicates the state of SOC27 conversions.

0 No sample pending for SOC11.
1 Trigger has been received and sample is pending for SOC11.

This bit will be automatically cleared when the SOC11 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

26SOC26R0hSOC26 Start of Conversion Flag. Indicates the state of SOC26 conversions.

0 No sample pending for SOC10.
1 Trigger has been received and sample is pending for SOC10.

This bit will be automatically cleared when the SOC10 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

25SOC25R0hSOC25 Start of Conversion Flag. Indicates the state of SOC25 conversions.

0 No sample pending for SOC9.
1 Trigger has been received and sample is pending for SOC9.

This bit will be automatically cleared when the SOC9 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

24SOC24R0hSOC24 Start of Conversion Flag. Indicates the state of SOC24 conversions.

0 No sample pending for SOC8.
1 Trigger has been received and sample is pending for SOC8.

This bit will be automatically cleared when the SOC8 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

23SOC23R0hSOC23 Start of Conversion Flag. Indicates the state of SO23 conversions.

0 No sample pending for SOC7.
1 Trigger has been received and sample is pending for SOC7.

This bit will be automatically cleared when the SOC7 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

22SOC22R0hSOC22 Start of Conversion Flag. Indicates the state of SOC22 conversions.

0 No sample pending for SOC6.
1 Trigger has been received and sample is pending for SOC6.

This bit will be automatically cleared when the SOC6 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

21SOC21R0hSOC21 Start of Conversion Flag. Indicates the state of SOC21 conversions.

0 No sample pending for SOC5.
1 Trigger has been received and sample is pending for SOC5.

This bit will be automatically cleared when the SOC5 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

20SOC20R0hSOC20 Start of Conversion Flag. Indicates the state of SOC20 conversions.

0 No sample pending for SOC4.
1 Trigger has been received and sample is pending for SOC4.

This bit will be automatically cleared when the SOC4 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

19SOC19R0hSOC19 Start of Conversion Flag. Indicates the state of SOC19 conversions.

0 No sample pending for SOC3.
1 Trigger has been received and sample is pending for SOC3.

This bit will be automatically cleared when the SOC3 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

18SOC18R0hSOC18 Start of Conversion Flag. Indicates the state of SOC18 conversions.

0 No sample pending for SOC2.
1 Trigger has been received and sample is pending for SOC2.

This bit will be automatically cleared when the SOC2 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

17SOC17R0hSOC17 Start of Conversion Flag. Indicates the state of SOC17 conversions.

0 No sample pending for SOC1.
1 Trigger has been received and sample is pending for SOC1.

This bit will be automatically cleared when the SOC1 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

16SOC16R0hSOC16 Start of Conversion Flag. Indicates the state of SO16 conversions.

0 No sample pending for SOC0.
1 Trigger has been received and sample is pending for SOC0.

This bit will be automatically cleared when the SOC0 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

15SOC15R0hSOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions.

0 No sample pending for SOC15.
1 Trigger has been received and sample is pending for SOC15.

This bit will be automatically cleared when the SOC15 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

14SOC14R0hSOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions.

0 No sample pending for SOC14.
1 Trigger has been received and sample is pending for SOC14.

This bit will be automatically cleared when the SOC14 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

13SOC13R0hSOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions.

0 No sample pending for SOC13.
1 Trigger has been received and sample is pending for SOC13.

This bit will be automatically cleared when the SOC13 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

12SOC12R0hSOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions.

0 No sample pending for SOC12.
1 Trigger has been received and sample is pending for SOC12.

This bit will be automatically cleared when the SOC12 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

11SOC11R0hSOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions.

0 No sample pending for SOC11.
1 Trigger has been received and sample is pending for SOC11.

This bit will be automatically cleared when the SOC11 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

10SOC10R0hSOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions.

0 No sample pending for SOC10.
1 Trigger has been received and sample is pending for SOC10.

This bit will be automatically cleared when the SOC10 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

9SOC9R0hSOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions.

0 No sample pending for SOC9.
1 Trigger has been received and sample is pending for SOC9.

This bit will be automatically cleared when the SOC9 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

8SOC8R0hSOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions.

0 No sample pending for SOC8.
1 Trigger has been received and sample is pending for SOC8.

This bit will be automatically cleared when the SOC8 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

7SOC7R0hSOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions.

0 No sample pending for SOC7.
1 Trigger has been received and sample is pending for SOC7.

This bit will be automatically cleared when the SOC7 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

6SOC6R0hSOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions.

0 No sample pending for SOC6.
1 Trigger has been received and sample is pending for SOC6.

This bit will be automatically cleared when the SOC6 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

5SOC5R0hSOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions.

0 No sample pending for SOC5.
1 Trigger has been received and sample is pending for SOC5.

This bit will be automatically cleared when the SOC5 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

4SOC4R0hSOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions.

0 No sample pending for SOC4.
1 Trigger has been received and sample is pending for SOC4.

This bit will be automatically cleared when the SOC4 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

3SOC3R0hSOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions.

0 No sample pending for SOC3.
1 Trigger has been received and sample is pending for SOC3.

This bit will be automatically cleared when the SOC3 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

2SOC2R0hSOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions.

0 No sample pending for SOC2.
1 Trigger has been received and sample is pending for SOC2.

This bit will be automatically cleared when the SOC2 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

1SOC1R0hSOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions.

0 No sample pending for SOC1.
1 Trigger has been received and sample is pending for SOC1.

This bit will be automatically cleared when the SOC1 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

0SOC0R0hSOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions.

0 No sample pending for SOC0.
1 Trigger has been received and sample is pending for SOC0.

This bit will be automatically cleared when the SOC0 conversion is started. If contention exists where this bit receives both a request to set and a request to clear on the same cycle, regardless of the source of either, this bit will be set and the request to clear will be ignored. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not.

Reset type: SYSRSn

24.16.3.14 ADCSOCFRC1 Register (Offset = 28h) [Reset = 00000000h]

ADCSOCFRC1 is shown in Figure 24-117 and described in Table 24-95.

Return to the Summary Table.

ADC SOC Force 1 Register

Figure 24-117 ADCSOCFRC1 Register
3130292827262524
SOC31SOC30SOC29SOC28SOC27SOC26SOC25SOC24
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
SOC23SOC22SOC21SOC20SOC19SOC18SOC17SOC16
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
SOC15SOC14SOC13SOC12SOC11SOC10SOC9SOC8
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
SOC7SOC6SOC5SOC4SOC3SOC2SOC1SOC0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 24-95 ADCSOCFRC1 Register Field Descriptions
BitFieldTypeResetDescription
31SOC31R-0/W1S0hSOC31 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC31 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC31 flag bit to 1. This will cause a conversion to start once priority is given to SOC31.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC31 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

30SOC30R-0/W1S0hSOC30 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC30 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC30 flag bit to 1. This will cause a conversion to start once priority is given to SOC30.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC30 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

29SOC29R-0/W1S0hSOC29 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC29 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC29 flag bit to 1. This will cause a conversion to start once priority is given to SOC29.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC29 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

28SOC28R-0/W1S0hSOC28 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC28 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC28 flag bit to 1. This will cause a conversion to start once priority is given to SOC28.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC28 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

27SOC27R-0/W1S0hSOC27 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC27 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC27 flag bit to 1. This will cause a conversion to start once priority is given to SOC27.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC27 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

26SOC26R-0/W1S0hSOC26 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC26 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC26 flag bit to 1. This will cause a conversion to start once priority is given to SOC26.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC26 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

25SOC25R-0/W1S0hSOC25 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC25 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC25 flag bit to 1. This will cause a conversion to start once priority is given to SOC25.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC25 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

24SOC24R-0/W1S0hSOC24 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC24 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC24 flag bit to 1. This will cause a conversion to start once priority is given to SOC24.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC24 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

23SOC23R-0/W1S0hSOC23 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC23 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC23 flag bit to 1. This will cause a conversion to start once priority is given to SOC23.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC23 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

22SOC22R-0/W1S0hSOC22 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC22 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC22 flag bit to 1. This will cause a conversion to start once priority is given to SOC22.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC22 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

21SOC21R-0/W1S0hSOC21 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC21 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC21 flag bit to 1. This will cause a conversion to start once priority is given to SOC21.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC21 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

20SOC20R-0/W1S0hSOC20 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC20 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC20 flag bit to 1. This will cause a conversion to start once priority is given to SOC20.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC20 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

19SOC19R-0/W1S0hSOC19 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC19 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC19 flag bit to 1. This will cause a conversion to start once priority is given to SOC19.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC19 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

18SOC18R-0/W1S0hSOC18 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC18 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC18 flag bit to 1. This will cause a conversion to start once priority is given to SOC18.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC18 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

17SOC17R-0/W1S0hSOC17 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC17 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC17 flag bit to 1. This will cause a conversion to start once priority is given to SOC17.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC17 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

16SOC16R-0/W1S0hSOC16 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC16 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC16 flag bit to 1. This will cause a conversion to start once priority is given to SOC16.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC16 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

15SOC15R-0/W1S0hSOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC15 flag bit to 1. This will cause a conversion to start once priority is given to SOC15.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC15 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

14SOC14R-0/W1S0hSOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC14 flag bit to 1. This will cause a conversion to start once priority is given to SOC14.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC14 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

13SOC13R-0/W1S0hSOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC13 flag bit to 1. This will cause a conversion to start once priority is given to SOC13.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC13 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

12SOC12R-0/W1S0hSOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC12 flag bit to 1. This will cause a conversion to start once priority is given to SOC12.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC12 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

11SOC11R-0/W1S0hSOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC11 flag bit to 1. This will cause a conversion to start once priority is given to SOC11.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC11 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

10SOC10R-0/W1S0hSOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC10 flag bit to 1. This will cause a conversion to start once priority is given to SOC10.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC10 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

9SOC9R-0/W1S0hSOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC9 flag bit to 1. This will cause a conversion to start once priority is given to SOC9.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC9 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

8SOC8R-0/W1S0hSOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC8 flag bit to 1. This will cause a conversion to start once priority is given to SOC8.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC8 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

7SOC7R-0/W1S0hSOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC7 flag bit to 1. This will cause a conversion to start once priority is given to SOC7.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC7 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

6SOC6R-0/W1S0hSOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC6 flag bit to 1. This will cause a conversion to start once priority is given to SOC6.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC6 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

5SOC5R-0/W1S0hSOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC5 flag bit to 1. This will cause a conversion to start once priority is given to SOC5.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC5 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

4SOC4R-0/W1S0hSOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC4 flag bit to 1. This will cause a conversion to start once priority is given to SOC4.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC4 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

3SOC3R-0/W1S0hSOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC3 flag bit to 1. This will cause a conversion to start once priority is given to SOC3.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC3 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

2SOC2R-0/W1S0hSOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC2 flag bit to 1. This will cause a conversion to start once priority is given to SOC2.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC2 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

1SOC1R-0/W1S0hSOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC1 flag bit to 1. This will cause a conversion to start once priority is given to SOC1.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC1 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

0SOC0R-0/W1S0hSOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0.

0 No action.
1 Force SOC0 flag bit to 1. This will cause a conversion to start once priority is given to SOC0.

If software tries to set this bit on the same clock cycle that hardware tries to clear the SOC0 bit in the ADCSOCFLG1 register, then software has priority and the ADCSOCFLG1 bit will be set. In this case the overflow bit in the ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not.

Reset type: SYSRSn

24.16.3.15 ADCSOCOVF1 Register (Offset = 2Ch) [Reset = 00000000h]

ADCSOCOVF1 is shown in Figure 24-118 and described in Table 24-96.

Return to the Summary Table.

ADC SOC Overflow 1 Register

Figure 24-118 ADCSOCOVF1 Register
3130292827262524
SOC31SOC30SOC29SOC28SOC27SOC26SOC25SOC24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
SOC23SOC22SOC21SOC20SOC19SOC18SOC17SOC16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
SOC15SOC14SOC13SOC12SOC11SOC10SOC9SOC8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
SOC7SOC6SOC5SOC4SOC3SOC2SOC1SOC0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 24-96 ADCSOCOVF1 Register Field Descriptions
BitFieldTypeResetDescription
31SOC31R0hSOC31 Start of Conversion Overflow Flag. Indicates an SOC31 event was generated in hardware while an existing SOC31 event was already pending.

0 No SOC31 event overflow.
1 SOC31 event overflow.

An overflow condition does not stop SOC31 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

30SOC30R0hSOC30 Start of Conversion Overflow Flag. Indicates an SOC30 event was generated in hardware while an existing SOC30 event was already pending.

0 No SOC30 event overflow.
1 SOC30 event overflow.

An overflow condition does not stop SOC30 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

29SOC29R0hSOC29 Start of Conversion Overflow Flag. Indicates an SOC29 event was generated in hardware while an existing SOC29 event was already pending.

0 No SOC29 event overflow.
1 SOC29 event overflow.

An overflow condition does not stop SOC29 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

28SOC28R0hSOC28 Start of Conversion Overflow Flag. Indicates an SOC28 event was generated in hardware while an existing SOC28 event was already pending.

0 No SOC28 event overflow.
1 SOC28 event overflow.

An overflow condition does not stop SOC28 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

27SOC27R0hSOC27 Start of Conversion Overflow Flag. Indicates an SOC27 event was generated in hardware while an existing SOC27 event was already pending.

0 No SOC27 event overflow.
1 SOC27 event overflow.

An overflow condition does not stop SOC27 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

26SOC26R0hSOC26 Start of Conversion Overflow Flag. Indicates an SOC26 event was generated in hardware while an existing SOC26 event was already pending.

0 No SOC26 event overflow.
1 SOC26 event overflow.

An overflow condition does not stop SOC26 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

25SOC25R0hSOC25 Start of Conversion Overflow Flag. Indicates an SOC25 event was generated in hardware while an existing SOC25 event was already pending.

0 No SOC25 event overflow.
1 SOC25 event overflow.

An overflow condition does not stop SOC25 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

24SOC24R0hSOC24 Start of Conversion Overflow Flag. Indicates an SOC24 event was generated in hardware while an existing SOC24 event was already pending.

0 No SOC24 event overflow.
1 SOC24 event overflow.

An overflow condition does not stop SOC24 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

23SOC23R0hSOC23 Start of Conversion Overflow Flag. Indicates an SOC23 event was generated in hardware while an existing SOC23 event was already pending.

0 No SOC23 event overflow.
1 SOC23 event overflow.

An overflow condition does not stop SOC23 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

22SOC22R0hSOC22 Start of Conversion Overflow Flag. Indicates an SOC22 event was generated in hardware while an existing SOC22 event was already pending.

0 No SOC22 event overflow.
1 SOC22 event overflow.

An overflow condition does not stop SOC22 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

21SOC21R0hSOC21 Start of Conversion Overflow Flag. Indicates an SOC21 event was generated in hardware while an existing SOC21 event was already pending.

0 No SOC21 event overflow.
1 SOC21 event overflow.

An overflow condition does not stop SOC21 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

20SOC20R0hSOC20 Start of Conversion Overflow Flag. Indicates an SOC20 event was generated in hardware while an existing SOC20 event was already pending.

0 No SOC20 event overflow.
1 SOC20 event overflow.

An overflow condition does not stop SOC20 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

19SOC19R0hSOC19 Start of Conversion Overflow Flag. Indicates an SOC19 event was generated in hardware while an existing SOC19 event was already pending.

0 No SOC19 event overflow.
1 SOC19 event overflow.

An overflow condition does not stop SOC19 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

18SOC18R0hSOC18 Start of Conversion Overflow Flag. Indicates an SOC18 event was generated in hardware while an existing SOC18 event was already pending.

0 No SOC18 event overflow.
1 SOC18 event overflow.

An overflow condition does not stop SOC18 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

17SOC17R0hSOC17 Start of Conversion Overflow Flag. Indicates an SOC17 event was generated in hardware while an existing SOC17 event was already pending.

0 No SOC17 event overflow.
1 SOC17 event overflow.

An overflow condition does not stop SOC17 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

16SOC16R0hSOC16 Start of Conversion Overflow Flag. Indicates an SOC16 event was generated in hardware while an existing SOC16 event was already pending.

0 No SOC16 event overflow.
1 SOC16 event overflow.

An overflow condition does not stop SOC16 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

15SOC15R0hSOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending.

0 No SOC15 event overflow.
1 SOC15 event overflow.

An overflow condition does not stop SOC15 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

14SOC14R0hSOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending.

0 No SOC14 event overflow.
1 SOC14 event overflow.

An overflow condition does not stop SOC14 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

13SOC13R0hSOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending.

0 No SOC13 event overflow.
1 SOC13 event overflow.

An overflow condition does not stop SOC13 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

12SOC12R0hSOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending.

0 No SOC12 event overflow.
1 SOC12 event overflow.

An overflow condition does not stop SOC12 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

11SOC11R0hSOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending.

0 No SOC11 event overflow.
1 SOC11 event overflow.

An overflow condition does not stop SOC11 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

10SOC10R0hSOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending.

0 No SOC10 event overflow.
1 SOC10 event overflow.

An overflow condition does not stop SOC10 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

9SOC9R0hSOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending.

0 No SOC9 event overflow.
1 SOC9 event overflow.

An overflow condition does not stop SOC9 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

8SOC8R0hSOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending.

0 No SOC8 event overflow.
1 SOC8 event overflow.

An overflow condition does not stop SOC8 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

7SOC7R0hSOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending.

0 No SOC7 event overflow.
1 SOC7 event overflow.

An overflow condition does not stop SOC7 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

6SOC6R0hSOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending.

0 No SOC6 event overflow.
1 SOC6 event overflow.

An overflow condition does not stop SOC6 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

5SOC5R0hSOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending.

0 No SOC5 event overflow.
1 SOC5 event overflow.

An overflow condition does not stop SOC5 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

4SOC4R0hSOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending.

0 No SOC4 event overflow.
1 SOC4 event overflow.

An overflow condition does not stop SOC4 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

3SOC3R0hSOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending.

0 No SOC3 event overflow.
1 SOC3 event overflow.

An overflow condition does not stop SOC3 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

2SOC2R0hSOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending.

0 No SOC2 event overflow.
1 SOC2 event overflow.

An overflow condition does not stop SOC2 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

1SOC1R0hSOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending.

0 No SOC1 event overflow.
1 SOC1 event overflow.

An overflow condition does not stop SOC1 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

0SOC0R0hSOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending.

0 No SOC0 event overflow.
1 SOC0 event overflow.

An overflow condition does not stop SOC0 events from being processed. It simply is an indication that a hardware trigger was missed. A write to the ADCSOCFRC1 register does not affect this bit.

Reset type: SYSRSn

24.16.3.16 ADCSOCOVFCLR1 Register (Offset = 30h) [Reset = 00000000h]

ADCSOCOVFCLR1 is shown in Figure 24-119 and described in Table 24-97.

Return to the Summary Table.

ADC SOC Overflow Clear 1 Register

Figure 24-119 ADCSOCOVFCLR1 Register
3130292827262524
SOC31SOC30SOC29SOC28SOC27SOC26SOC25SOC24
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
2322212019181716
SOC23SOC22SOC21SOC20SOC19SOC18SOC17SOC16
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
15141312111098
SOC15SOC14SOC13SOC12SOC11SOC10SOC9SOC8
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
SOC7SOC6SOC5SOC4SOC3SOC2SOC1SOC0
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 24-97 ADCSOCOVFCLR1 Register Field Descriptions
BitFieldTypeResetDescription
31SOC31R-0/W1S0hSOC31 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC31 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC31 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

30SOC30R-0/W1S0hSOC30 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC30 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC30 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

29SOC29R-0/W1S0hSOC29 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC29 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC29 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

28SOC28R-0/W1S0hSOC28 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC28 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC28 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

27SOC27R-0/W1S0hSOC27 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC27 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC27 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

26SOC26R-0/W1S0hSOC26 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC26 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC26 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

25SOC25R-0/W1S0hSOC25 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC25 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC25 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

24SOC24R-0/W1S0hSOC24 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC24 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC24 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

23SOC23R-0/W1S0hSOC23 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC23 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC23 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

22SOC22R-0/W1S0hSOC22 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC22 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC22 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

21SOC21R-0/W1S0hSOC21 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC21 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC21 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

20SOC20R-0/W1S0hSOC20 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC20 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC20 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

19SOC19R-0/W1S0hSOC19 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC19 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC19 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

18SOC18R-0/W1S0hSOC18 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC18 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC18 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

17SOC17R-0/W1S0hSOC17 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC17 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC17 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

16SOC16R-0/W1S0hSOC16 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC16 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC16 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

15SOC15R-0/W1S0hSOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC15 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

14SOC14R-0/W1S0hSOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC14 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

13SOC13R-0/W1S0hSOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC13 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

12SOC12R-0/W1S0hSOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC12 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

11SOC11R-0/W1S0hSOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC11 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

10SOC10R-0/W1S0hSOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC10 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

9SOC9R-0/W1S0hSOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC9 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

8SOC8R-0/W1S0hSOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC8 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

7SOC7R-0/W1S0hSOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC7 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

6SOC6R-0/W1S0hSOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC6 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

5SOC5R-0/W1S0hSOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC5 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

4SOC4R-0/W1S0hSOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC4 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

3SOC3R-0/W1S0hSOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC3 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

2SOC2R-0/W1S0hSOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC2 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

1SOC1R-0/W1S0hSOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC1 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

0SOC0R-0/W1S0hSOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0.

0 No action.
1 Clear SOC0 overflow flag.

If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set..

Reset type: SYSRSn

24.16.3.17 ADCSOC0CTL Register (Offset = 34h) [Reset = 00000000h]

ADCSOC0CTL is shown in Figure 24-120 and described in Table 24-98.

Return to the Summary Table.

ADC SOC0 Control Register

Figure 24-120 ADCSOC0CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-98 ADCSOC0CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC0 External Channel Mux Select. Selects the external mux combination to output when SOC0 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC0 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.18 ADCSOC1CTL Register (Offset = 38h) [Reset = 00000000h]

ADCSOC1CTL is shown in Figure 24-121 and described in Table 24-99.

Return to the Summary Table.

ADC SOC1 Control Register

Figure 24-121 ADCSOC1CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-99 ADCSOC1CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC1 External Channel Mux Select. Selects the external mux combination to output when SOC1 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC1 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.19 ADCSOC2CTL Register (Offset = 3Ch) [Reset = 00000000h]

ADCSOC2CTL is shown in Figure 24-122 and described in Table 24-100.

Return to the Summary Table.

ADC SOC2 Control Register

Figure 24-122 ADCSOC2CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-100 ADCSOC2CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC2 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.20 ADCSOC3CTL Register (Offset = 40h) [Reset = 00000000h]

ADCSOC3CTL is shown in Figure 24-123 and described in Table 24-101.

Return to the Summary Table.

ADC SOC3 Control Register

Figure 24-123 ADCSOC3CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-101 ADCSOC3CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC3 External Channel Mux Select. Selects the external mux combination to output when SOC3 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC3 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.21 ADCSOC4CTL Register (Offset = 44h) [Reset = 00000000h]

ADCSOC4CTL is shown in Figure 24-124 and described in Table 24-102.

Return to the Summary Table.

ADC SOC4 Control Register

Figure 24-124 ADCSOC4CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-102 ADCSOC4CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC4 External Channel Mux Select. Selects the external mux combination to output when SOC4 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC4 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.22 ADCSOC5CTL Register (Offset = 48h) [Reset = 00000000h]

ADCSOC5CTL is shown in Figure 24-125 and described in Table 24-103.

Return to the Summary Table.

ADC SOC5 Control Register

Figure 24-125 ADCSOC5CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-103 ADCSOC5CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC5 External Channel Mux Select. Selects the external mux combination to output when SOC5 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC5 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.23 ADCSOC6CTL Register (Offset = 4Ch) [Reset = 00000000h]

ADCSOC6CTL is shown in Figure 24-126 and described in Table 24-104.

Return to the Summary Table.

ADC SOC6 Control Register

Figure 24-126 ADCSOC6CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-104 ADCSOC6CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC6 External Channel Mux Select. Selects the external mux combination to output when SOC6 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC6 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.24 ADCSOC7CTL Register (Offset = 50h) [Reset = 00000000h]

ADCSOC7CTL is shown in Figure 24-127 and described in Table 24-105.

Return to the Summary Table.

ADC SOC7 Control Register

Figure 24-127 ADCSOC7CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-105 ADCSOC7CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC7 External Channel Mux Select. Selects the external mux combination to output when SOC7 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC7 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.25 ADCSOC8CTL Register (Offset = 54h) [Reset = 00000000h]

ADCSOC8CTL is shown in Figure 24-128 and described in Table 24-106.

Return to the Summary Table.

ADC SOC8 Control Register

Figure 24-128 ADCSOC8CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-106 ADCSOC8CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC8 External Channel Mux Select. Selects the external mux combination to output when SOC8 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC8 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.26 ADCSOC9CTL Register (Offset = 58h) [Reset = 00000000h]

ADCSOC9CTL is shown in Figure 24-129 and described in Table 24-107.

Return to the Summary Table.

ADC SOC9 Control Register

Figure 24-129 ADCSOC9CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-107 ADCSOC9CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC9 External Channel Mux Select. Selects the external mux combination to output when SOC9 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC9 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.27 ADCSOC10CTL Register (Offset = 5Ch) [Reset = 00000000h]

ADCSOC10CTL is shown in Figure 24-130 and described in Table 24-108.

Return to the Summary Table.

ADC SOC10 Control Register

Figure 24-130 ADCSOC10CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-108 ADCSOC10CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC10 External Channel Mux Select. Selects the external mux combination to output when SOC10 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC10 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.28 ADCSOC11CTL Register (Offset = 60h) [Reset = 00000000h]

ADCSOC11CTL is shown in Figure 24-131 and described in Table 24-109.

Return to the Summary Table.

ADC SOC11 Control Register

Figure 24-131 ADCSOC11CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-109 ADCSOC11CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC11 External Channel Mux Select. Selects the external mux combination to output when SOC11 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC11 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.29 ADCSOC12CTL Register (Offset = 64h) [Reset = 00000000h]

ADCSOC12CTL is shown in Figure 24-132 and described in Table 24-110.

Return to the Summary Table.

ADC SOC12 Control Register

Figure 24-132 ADCSOC12CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-110 ADCSOC12CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC12 External Channel Mux Select. Selects the external mux combination to output when SOC12 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC12 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.30 ADCSOC13CTL Register (Offset = 68h) [Reset = 00000000h]

ADCSOC13CTL is shown in Figure 24-133 and described in Table 24-111.

Return to the Summary Table.

ADC SOC13 Control Register

Figure 24-133 ADCSOC13CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-111 ADCSOC13CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC13 External Channel Mux Select. Selects the external mux combination to output when SOC13 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC13 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.31 ADCSOC14CTL Register (Offset = 6Ch) [Reset = 00000000h]

ADCSOC14CTL is shown in Figure 24-134 and described in Table 24-112.

Return to the Summary Table.

ADC SOC14 Control Register

Figure 24-134 ADCSOC14CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-112 ADCSOC14CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC14 External Channel Mux Select. Selects the external mux combination to output when SOC14 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC14 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.32 ADCSOC15CTL Register (Offset = 70h) [Reset = 00000000h]

ADCSOC15CTL is shown in Figure 24-135 and described in Table 24-113.

Return to the Summary Table.

ADC SOC15 Control Register

Figure 24-135 ADCSOC15CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-113 ADCSOC15CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC15 External Channel Mux Select. Selects the external mux combination to output when SOC15 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC15 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.33 ADCSOC16CTL Register (Offset = 74h) [Reset = 00000000h]

ADCSOC16CTL is shown in Figure 24-136 and described in Table 24-114.

Return to the Summary Table.

ADC SOC16 Control Register

Figure 24-136 ADCSOC16CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-114 ADCSOC16CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC16 External Channel Mux Select. Selects the external mux combination to output when SOC16 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC16 Trigger Source Select. Along with the SOC16 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC16 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC16 Channel Select. Selects the channel to be converted when SOC16 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC16 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.34 ADCSOC17CTL Register (Offset = 78h) [Reset = 00000000h]

ADCSOC17CTL is shown in Figure 24-137 and described in Table 24-115.

Return to the Summary Table.

ADC SOC17 Control Register

Figure 24-137 ADCSOC17CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-115 ADCSOC17CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC17 External Channel Mux Select. Selects the external mux combination to output when SOC17 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC17 Trigger Source Select. Along with the SOC17 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC17 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC17 Channel Select. Selects the channel to be converted when SOC17 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC17 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.35 ADCSOC18CTL Register (Offset = 7Ch) [Reset = 00000000h]

ADCSOC18CTL is shown in Figure 24-138 and described in Table 24-116.

Return to the Summary Table.

ADC SOC18 Control Register

Figure 24-138 ADCSOC18CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-116 ADCSOC18CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC18 External Channel Mux Select. Selects the external mux combination to output when SOC18 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC18 Trigger Source Select. Along with the SOC18 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC18 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC18 Channel Select. Selects the channel to be converted when SOC18 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC18 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.36 ADCSOC19CTL Register (Offset = 80h) [Reset = 00000000h]

ADCSOC19CTL is shown in Figure 24-139 and described in Table 24-117.

Return to the Summary Table.

ADC SOC19 Control Register

Figure 24-139 ADCSOC19CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-117 ADCSOC19CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC19 External Channel Mux Select. Selects the external mux combination to output when SOC19 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC19 Trigger Source Select. Along with the SOC19 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC19 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC19 Channel Select. Selects the channel to be converted when SOC19 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC19 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.37 ADCSOC20CTL Register (Offset = 84h) [Reset = 00000000h]

ADCSOC20CTL is shown in Figure 24-140 and described in Table 24-118.

Return to the Summary Table.

ADC SOC20 Control Register

Figure 24-140 ADCSOC20CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-118 ADCSOC20CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC20 External Channel Mux Select. Selects the external mux combination to output when SOC20 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC20 Trigger Source Select. Along with the SOC20 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC20 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC20 Channel Select. Selects the channel to be converted when SOC20 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC20 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.38 ADCSOC21CTL Register (Offset = 88h) [Reset = 00000000h]

ADCSOC21CTL is shown in Figure 24-141 and described in Table 24-119.

Return to the Summary Table.

ADC SOC21 Control Register

Figure 24-141 ADCSOC21CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-119 ADCSOC21CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC21 External Channel Mux Select. Selects the external mux combination to output when SOC21 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC21 Trigger Source Select. Along with the SOC21 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC21 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC21 Channel Select. Selects the channel to be converted when SOC21 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC21 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.39 ADCSOC22CTL Register (Offset = 8Ch) [Reset = 00000000h]

ADCSOC22CTL is shown in Figure 24-142 and described in Table 24-120.

Return to the Summary Table.

ADC SOC22 Control Register

Figure 24-142 ADCSOC22CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-120 ADCSOC22CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC22 External Channel Mux Select. Selects the external mux combination to output when SOC22 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC22 Trigger Source Select. Along with the SOC22 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC22 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC22 Channel Select. Selects the channel to be converted when SOC22 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC22 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.40 ADCSOC23CTL Register (Offset = 90h) [Reset = 00000000h]

ADCSOC23CTL is shown in Figure 24-143 and described in Table 24-121.

Return to the Summary Table.

ADC SOC23 Control Register

Figure 24-143 ADCSOC23CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-121 ADCSOC23CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC23 External Channel Mux Select. Selects the external mux combination to output when SOC23 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC23 Trigger Source Select. Along with the SOC23 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC23 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC23 Channel Select. Selects the channel to be converted when SOC23 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC23 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.41 ADCSOC24CTL Register (Offset = 94h) [Reset = 00000000h]

ADCSOC24CTL is shown in Figure 24-144 and described in Table 24-122.

Return to the Summary Table.

ADC SOC24 Control Register

Figure 24-144 ADCSOC24CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-122 ADCSOC24CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC24 External Channel Mux Select. Selects the external mux combination to output when SOC24 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC24 Trigger Source Select. Along with the SOC24 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC24 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC24 Channel Select. Selects the channel to be converted when SOC24 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC24 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.42 ADCSOC25CTL Register (Offset = 98h) [Reset = 00000000h]

ADCSOC25CTL is shown in Figure 24-145 and described in Table 24-123.

Return to the Summary Table.

ADC SOC25 Control Register

Figure 24-145 ADCSOC25CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-123 ADCSOC25CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC25 External Channel Mux Select. Selects the external mux combination to output when SOC25 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC25 Trigger Source Select. Along with the SOC25 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC25 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC25 Channel Select. Selects the channel to be converted when SOC25 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC25 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.43 ADCSOC26CTL Register (Offset = 9Ch) [Reset = 00000000h]

ADCSOC26CTL is shown in Figure 24-146 and described in Table 24-124.

Return to the Summary Table.

ADC SOC26 Control Register

Figure 24-146 ADCSOC26CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-124 ADCSOC26CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC26 External Channel Mux Select. Selects the external mux combination to output when SOC26 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC26 Trigger Source Select. Along with the SOC26 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC26 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC26 Channel Select. Selects the channel to be converted when SOC26 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC26 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.44 ADCSOC27CTL Register (Offset = A0h) [Reset = 00000000h]

ADCSOC27CTL is shown in Figure 24-147 and described in Table 24-125.

Return to the Summary Table.

ADC SOC27 Control Register

Figure 24-147 ADCSOC27CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-125 ADCSOC27CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC27 External Channel Mux Select. Selects the external mux combination to output when SOC27 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC27 Trigger Source Select. Along with the SOC27 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC27 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC27 Channel Select. Selects the channel to be converted when SOC27 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC27 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.45 ADCSOC28CTL Register (Offset = A4h) [Reset = 00000000h]

ADCSOC28CTL is shown in Figure 24-148 and described in Table 24-126.

Return to the Summary Table.

ADC SOC28 Control Register

Figure 24-148 ADCSOC28CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-126 ADCSOC28CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC28 External Channel Mux Select. Selects the external mux combination to output when SOC28 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC28 Trigger Source Select. Along with the SOC28 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC28 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC28 Channel Select. Selects the channel to be converted when SOC28 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC28 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.46 ADCSOC29CTL Register (Offset = A8h) [Reset = 00000000h]

ADCSOC29CTL is shown in Figure 24-149 and described in Table 24-127.

Return to the Summary Table.

ADC SOC29 Control Register

Figure 24-149 ADCSOC29CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-127 ADCSOC29CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC29 External Channel Mux Select. Selects the external mux combination to output when SOC29 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC29 Trigger Source Select. Along with the SOC29 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC29 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC29 Channel Select. Selects the channel to be converted when SOC29 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC29 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.47 ADCSOC30CTL Register (Offset = ACh) [Reset = 00000000h]

ADCSOC30CTL is shown in Figure 24-150 and described in Table 24-128.

Return to the Summary Table.

ADC SOC30 Control Register

Figure 24-150 ADCSOC30CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-128 ADCSOC30CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC30 External Channel Mux Select. Selects the external mux combination to output when SOC30 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC30 Trigger Source Select. Along with the SOC30 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC30 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC30 Channel Select. Selects the channel to be converted when SOC30 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC30 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.48 ADCSOC31CTL Register (Offset = B0h) [Reset = 00000000h]

ADCSOC31CTL is shown in Figure 24-151 and described in Table 24-129.

Return to the Summary Table.

ADC SOC31 Control Register

Figure 24-151 ADCSOC31CTL Register
3130292827262524
EXTCHSELRESERVEDTRIGSEL
R/W-0hR-0hR/W-0h
2322212019181716
TRIGSELCHSEL
R/W-0hR/W-0h
15141312111098
CHSELRESERVEDRESERVEDRESERVEDACQPS
R/W-0hR/W-0hR/W-0hR-0hR/W-0h
76543210
ACQPS
R/W-0h
Table 24-129 ADCSOC31CTL Register Field Descriptions
BitFieldTypeResetDescription
31-28EXTCHSELR/W0hSOC31 External Channel Mux Select. Selects the external mux combination to output when SOC31 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.

0h ADCEXTMUX[3:0] = 0000
1h ADCEXTMUX[3:0] = 0001
2h ADCEXTMUX[3:0] = 0010
3h ADCEXTMUX[3:0] = 0011
4h ADCEXTMUX[3:0] = 0100
5h ADCEXTMUX[3:0] = 0101
6h ADCEXTMUX[3:0] = 0110
7h ADCEXTMUX[3:0] = 0111
8h ADCEXTMUX[3:0] = 1000
9h ADCEXTMUX[3:0] = 1001
Ah ADCEXTMUX[3:0] = 1010
Bh ADCEXTMUX[3:0] = 1011
Ch ADCEXTMUX[3:0] = 1100
Dh ADCEXTMUX[3:0] = 1101
Eh ADCEXTMUX[3:0] = 1110
Fh ADCEXTMUX[3:0] = 1111

Reset type: SYSRSn

27RESERVEDR0hReserved
26-20TRIGSELR/W0hSOC31 Trigger Source Select. Along with the SOC31 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC31 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it.

Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration.

00h ADCTRIG0 - Software only
01h-7fh ADCTRIG1-ADCTRG127 - Hardware trigger sources

Reset type: SYSRSn

19-15CHSELR/W0hSOC31 Channel Select. Selects the channel to be converted when SOC31 is received by the ADC.

Single-ended Signaling Mode (SIGNALMODE = 0):
00h ADCIN0
01h ADCIN1
02h ADCIN2
03h ADCIN3
...
1Dh ADCIN29
1Eh ADCIN30
1Fh ADCIN31

Differential Signaling Mode (SIGNALMODE = 1):
00h ADCIN0 (non-inverting) and ADCIN1 (inverting)
01h ADCIN0 (non-inverting) and ADCIN1 (inverting)
02h ADCIN2 (non-inverting) and ADCIN3 (inverting)
03h ADCIN2 (non-inverting) and ADCIN3 (inverting)
04h ADCIN4 (non-inverting) and ADCIN5 (inverting)
05h ADCIN4 (non-inverting) and ADCIN5 (inverting)
...
0Eh ADCIN26 (non-inverting) and ADCIN27 (inverting)
0Fh ADCIN26 (non-inverting) and ADCIN27 (inverting)
10h ADCIN28 (non-inverting) and ADCIN29 (inverting)
11h ADCIN28 (non-inverting) and ADCIN29 (inverting)
1Eh ADCIN30 (non-inverting) and ADCIN31 (inverting)
1Fh ADCIN30 (non-inverting) and ADCIN31 (inverting)

Reset type: SYSRSn

14-12RESERVEDR/W0hReserved
11-10RESERVEDR/W0hReserved
9RESERVEDR0hReserved
8-0ACQPSR/W0hSOC31 Acquisition Prescale. Controls the sample and hold window for this SOC.

000h Reserved
001h Reserved
002h Sample window is 3 system clock cycles wide
003h Sample window is 4 system clock cycles wide
...
1FFh Sample window is 512 system clock cycles wide

The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.

Reset type: SYSRSn

24.16.3.49 ADCEVTSTAT Register (Offset = B4h) [Reset = 0000h]

ADCEVTSTAT is shown in Figure 24-152 and described in Table 24-130.

Return to the Summary Table.

ADC Event Status Register

Figure 24-152 ADCEVTSTAT Register
15141312111098
RESERVEDPPB4ZEROPPB4TRIPLOPPB4TRIPHIRESERVEDPPB3ZEROPPB3TRIPLOPPB3TRIPHI
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDPPB2ZEROPPB2TRIPLOPPB2TRIPHIRESERVEDPPB1ZEROPPB1TRIPLOPPB1TRIPHI
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 24-130 ADCEVTSTAT Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14PPB4ZEROR0hPost Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

13PPB4TRIPLOR0hPost Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

12PPB4TRIPHIR0hPost Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

11RESERVEDR0hReserved
10PPB3ZEROR0hPost Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

9PPB3TRIPLOR0hPost Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

8PPB3TRIPHIR0hPost Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

7RESERVEDR0hReserved
6PPB2ZEROR0hPost Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

5PPB2TRIPLOR0hPost Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

4PPB2TRIPHIR0hPost Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

3RESERVEDR0hReserved
2PPB1ZEROR0hPost Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

1PPB1TRIPLOR0hPost Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

0PPB1TRIPHIR0hPost Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred.

Note: these bits are set even when the corresponding enable in ADCEVTINTSEL is not set. Because of this, an ISR may need to examine both the ADCEVTSTAT and ADCEVTINTSEL registers to determine the source of the interrupt.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

24.16.3.50 ADCEVTCLR Register (Offset = B8h) [Reset = 0000h]

ADCEVTCLR is shown in Figure 24-153 and described in Table 24-131.

Return to the Summary Table.

ADC Event Clear Register

Figure 24-153 ADCEVTCLR Register
15141312111098
RESERVEDPPB4ZEROPPB4TRIPLOPPB4TRIPHIRESERVEDPPB3ZEROPPB3TRIPLOPPB3TRIPHI
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
76543210
RESERVEDPPB2ZEROPPB2TRIPLOPPB2TRIPHIRESERVEDPPB1ZEROPPB1TRIPLOPPB1TRIPHI
R-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 24-131 ADCEVTCLR Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14PPB4ZEROR-0/W1S0hPost Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

13PPB4TRIPLOR-0/W1S0hPost Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

12PPB4TRIPHIR-0/W1S0hPost Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

11RESERVEDR0hReserved
10PPB3ZEROR-0/W1S0hPost Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

9PPB3TRIPLOR-0/W1S0hPost Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

8PPB3TRIPHIR-0/W1S0hPost Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

7RESERVEDR0hReserved
6PPB2ZEROR-0/W1S0hPost Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

5PPB2TRIPLOR-0/W1S0hPost Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

4PPB2TRIPHIR-0/W1S0hPost Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

3RESERVEDR0hReserved
2PPB1ZEROR-0/W1S0hPost Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

1PPB1TRIPLOR-0/W1S0hPost Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

0PPB1TRIPHIR-0/W1S0hPost Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority

Reset type: SYSRSn

24.16.3.51 ADCEVTSEL Register (Offset = BCh) [Reset = 0000h]

ADCEVTSEL is shown in Figure 24-154 and described in Table 24-132.

Return to the Summary Table.

ADC Event Selection Register

Figure 24-154 ADCEVTSEL Register
15141312111098
RESERVEDPPB4ZEROPPB4TRIPLOPPB4TRIPHIRESERVEDPPB3ZEROPPB3TRIPLOPPB3TRIPHI
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDPPB2ZEROPPB2TRIPLOPPB2TRIPHIRESERVEDPPB1ZEROPPB1TRIPLOPPB1TRIPHI
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 24-132 ADCEVTSEL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14PPB4ZEROR/W0hPost Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

13PPB4TRIPLOR/W0hPost Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

12PPB4TRIPHIR/W0hPost Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

11RESERVEDR0hReserved
10PPB3ZEROR/W0hPost Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

9PPB3TRIPLOR/W0hPost Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

8PPB3TRIPHIR/W0hPost Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

7RESERVEDR0hReserved
6PPB2ZEROR/W0hPost Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

5PPB2TRIPLOR/W0hPost Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

4PPB2TRIPHIR/W0hPost Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

3RESERVEDR0hReserved
2PPB1ZEROR/W0hPost Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

1PPB1TRIPLOR/W0hPost Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

0PPB1TRIPHIR/W0hPost Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks.

Reset type: SYSRSn

24.16.3.52 ADCEVTINTSEL Register (Offset = C0h) [Reset = 0000h]

ADCEVTINTSEL is shown in Figure 24-155 and described in Table 24-133.

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ADC Event Interrupt Selection Register

Figure 24-155 ADCEVTINTSEL Register
15141312111098
RESERVEDPPB4ZEROPPB4TRIPLOPPB4TRIPHIRESERVEDPPB3ZEROPPB3TRIPLOPPB3TRIPHI
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDPPB2ZEROPPB2TRIPLOPPB2TRIPHIRESERVEDPPB1ZEROPPB1TRIPLOPPB1TRIPHI
R-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 24-133 ADCEVTINTSEL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14PPB4ZEROR/W0hPost Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

13PPB4TRIPLOR/W0hPost Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

12PPB4TRIPHIR/W0hPost Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

11RESERVEDR0hReserved
10PPB3ZEROR/W0hPost Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

9PPB3TRIPLOR/W0hPost Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

8PPB3TRIPHIR/W0hPost Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

7RESERVEDR0hReserved
6PPB2ZEROR/W0hPost Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

5PPB2TRIPLOR/W0hPost Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

4PPB2TRIPHIR/W0hPost Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

3RESERVEDR0hReserved
2PPB1ZEROR/W0hPost Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

1PPB1TRIPLOR/W0hPost Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

0PPB1TRIPHIR/W0hPost Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE.

Reset type: SYSRSn

24.16.3.53 ADCOSDETECT Register (Offset = C4h) [Reset = 0000h]

ADCOSDETECT is shown in Figure 24-156 and described in Table 24-134.

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ADC Open and Shorts Detect Register

Figure 24-156 ADCOSDETECT Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDDETECTCFG
R-0hR/W-0h
Table 24-134 ADCOSDETECT Register Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDR0hReserved
2-0DETECTCFGR/W0hADC Opens and Shorts Detect Configuration. This bit field defines the open/shorts detection circuit state.

0h Open/Shorts detection circuit is disabled.
1h Open/Shorts detection circuit is enabled at zero scale.
2h Open/Shorts detection circuit is enabled at full scale.
3h Open/Shorts detection circuit is enabled at (nominal) 5/12 scale.
4h Open/Shorts detection circuit is enabled at (nominal) 7/12 scale.
5h Open/Shorts detection circuit is enabled with a (nominal) 5K pulldown to VSSA.
6h Open/Shorts detection circuit is enabled with a (nominal) 5K pullup to VDDA.
7h Open/Shorts detection circuit is enabled with a (nominal) 7K pulldown to VSSA.

Reset type: SYSRSn

24.16.3.54 ADCCOUNTER Register (Offset = C6h) [Reset = 0000h]

ADCCOUNTER is shown in Figure 24-157 and described in Table 24-135.

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ADC Counter Register

Figure 24-157 ADCCOUNTER Register
15141312111098
RESERVEDFREECOUNT
R-0hR-0h
76543210
FREECOUNT
R-0h
Table 24-135 ADCCOUNTER Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0hReserved
11-0FREECOUNTR0hADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter.

Reset type: SYSRSn

24.16.3.55 ADCREV Register (Offset = C8h) [Reset = 0105h]

ADCREV is shown in Figure 24-158 and described in Table 24-136.

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ADC Revision Register

Figure 24-158 ADCREV Register
15141312111098
REV
R-1h
76543210
TYPE
R-5h
Table 24-136 ADCREV Register Field Descriptions
BitFieldTypeResetDescription
15-8REVR1hADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h.

Reset type: SYSRSn

7-0TYPER5hADC Type. Always set to 5 for this ADC.

Reset type: SYSRSn

24.16.3.56 ADCOFFTRIM Register (Offset = CAh) [Reset = 0000h]

ADCOFFTRIM is shown in Figure 24-159 and described in Table 24-137.

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ADC Offset Trim Register 1

Figure 24-159 ADCOFFTRIM Register
15141312111098
OFFTRIM12BSEODD
R/W-0h
76543210
OFFTRIM
R/W-0h
Table 24-137 ADCOFFTRIM Register Field Descriptions
BitFieldTypeResetDescription
15-8OFFTRIM12BSEODDR/W0hIf ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 12-bit single-ended mode for odd channels.

Range is +127 steps to -128 steps (2's compliment format).

Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536.

Reset type: XRSn

7-0OFFTRIMR/W0hADC Offset Trim. Adjusts the conversion results of the converter up or down to account for offset error in the ADC. A different offset trim is required for each combination of resolution and signal mode. If ADCCTL2.OFFTRIMMODE = 0, then using the AdcSetMode function to set the resolution and signal mode will ensure that the correct offset trim is loaded into this register. If ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim only when the ADC is in 12-bit single-ended mode and only for even channels.

Range is +127 steps to -128 steps (2's compliment format).

Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536.

Reset type: XRSn

24.16.3.57 ADCOFFTRIM2 Register (Offset = CCh) [Reset = 0000h]

ADCOFFTRIM2 is shown in Figure 24-160 and described in Table 24-138.

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ADC Offset Trim Register 2

Figure 24-160 ADCOFFTRIM2 Register
15141312111098
OFFTRIM16BSEODD
R/W-0h
76543210
OFFTRIM16BSEEVEN
R/W-0h
Table 24-138 ADCOFFTRIM2 Register Field Descriptions
BitFieldTypeResetDescription
15-8OFFTRIM16BSEODDR/W0hIf ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 16-bit single-ended mode for odd channels.

Range is +127 steps to -128 steps (2's compliment format).

Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536.

Reset type: XRSn

7-0OFFTRIM16BSEEVENR/W0hIf ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 16-bit single-ended mode for even channels.

Range is +127 steps to -128 steps (2's compliment format).

Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536.

Reset type: XRSn

24.16.3.58 ADCOFFTRIM3 Register (Offset = CEh) [Reset = 0000h]

ADCOFFTRIM3 is shown in Figure 24-161 and described in Table 24-139.

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ADC Offset Trim Register 3

Figure 24-161 ADCOFFTRIM3 Register
15141312111098
OFFTRIM16BDE
R/W-0h
76543210
OFFTRIM12BDE
R/W-0h
Table 24-139 ADCOFFTRIM3 Register Field Descriptions
BitFieldTypeResetDescription
15-8OFFTRIM16BDER/W0hIf ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 16-bit differential mode.

Range is +127 steps to -128 steps (2's compliment format).

Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536.

Reset type: XRSn

7-0OFFTRIM12BDER/W0hIf ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 12-bit differential mode.

Range is +127 steps to -128 steps (2's compliment format).

Regardless of the converter resolution, the size of each trim step is (VREFHI-VREFLO)/65536.

Reset type: XRSn

24.16.3.59 ADCPPB1CONFIG Register (Offset = D4h) [Reset = 0000h]

ADCPPB1CONFIG is shown in Figure 24-162 and described in Table 24-140.

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ADC PPB{#} Config Register

Figure 24-162 ADCPPB1CONFIG Register
15141312111098
RESERVEDDELTAEN
R-0hR/W-0h
76543210
TWOSCOMPENABSENCBCENCONFIG
R/W-0hR/W-0hR/W-0hR/W-0h
Table 24-140 ADCPPB1CONFIG Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0hReserved
8DELTAENR/W0hADC Post Processing Block 1 enable delta (difference) from last sample calcualtion. When set, the ADCPPB1RESULT register will contain the difference between the most recent conversion result and the last value that would have been loaded into the ADCPPB1RESULT (if the delta calculation wasn't enabled).

The delta calculation occurs after OFFREF, TWOSCOMPEN, and ABSEN calculations are applied.

0 Delta calculation disabled: no modification to ADCPPB1RESULT
1 ADCPPB1RESULT = ADCPPB1RESULT'[t] - ADCPPB1RESULT'[t - 1]

Where ADCPPB1RESULT' is the value that would have been loaded into ADCPPB1RESULT without delta calculation

Reset type: SYSRSn

7TWOSCOMPENR/W0hADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB1RESULT register.

0 ADCPPB1RESULT = ADCRESULTx - ADCPPB1OFFREF
1 ADCPPB1RESULT = ADCPPB1OFFREF - ADCRESULTx

Reset type: SYSRSn

6ABSENR/W0hADC Post Processing Block 1 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB1.

This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT)

0 ADCPPB1RESULT = ADCRESULTx - ADCPPB1OFFREF
1 ADCPPB1RESULT = abs(ADCRESULTx - ADCPPB1OFFREF)

Reset type: SYSRSn

5CBCENR/W0hADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present.

Reset type: SYSRSn

4-0CONFIGR/W0hADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block.

0x0 SOC0/EOC0/RESULT0 is associated with post processing block 1
0x1 SOC1/EOC1/RESULT1 is associated with post processing block 1
0x2 SOC2/EOC2/RESULT2 is associated with post processing block 1
0x3 SOC3/EOC3/RESULT3 is associated with post processing block 1
0x4 SOC4/EOC4/RESULT4 is associated with post processing block 1
0x5 SOC5/EOC5/RESULT5 is associated with post processing block 1
0x6 SOC6/EOC6/RESULT6 is associated with post processing block 1
0x7 SOC7/EOC7/RESULT7 is associated with post processing block 1
0x8 SOC8/EOC8/RESULT8 is associated with post processing block 1
0x9 SOC9/EOC9/RESULT9 is associated with post processing block 1
0xA SOC10/EOC10/RESULT10 is associated with post processing block 1
0xB SOC11/EOC11/RESULT11 is associated with post processing block 1
0xC SOC12/EOC12/RESULT12 is associated with post processing block 1
0xD SOC13/EOC13/RESULT13 is associated with post processing block 1
0xE SOC14/EOC14/RESULT14 is associated with post processing block 1
0xF SOC15/EOC15/RESULT15 is associated with post processing block 1
0x0 SOC16/EOC16/RESULT16 is associated with post processing block 1
0x1 SOC17/EOC17/RESULT17 is associated with post processing block 1
0x2 SOC18/EOC18/RESULT18 is associated with post processing block 1
0x3 SOC19/EOC19/RESULT19 is associated with post processing block 1
0x4 SOC20/EOC20/RESULT20 is associated with post processing block 1
0x5 SOC21/EOC21/RESULT21 is associated with post processing block 1
0x6 SOC22/EOC22/RESULT22 is associated with post processing block 1
0x7 SOC23/EOC23/RESULT23 is associated with post processing block 1
0x8 SOC24/EOC24/RESULT24 is associated with post processing block 1
0x9 SOC25/EOC25/RESULT25 is associated with post processing block 1
0xA SOC26/EOC26/RESULT26 is associated with post processing block 1
0xB SOC27/EOC27/RESULT27 is associated with post processing block 1
0xC SOC28/EOC28/RESULT28 is associated with post processing block 1
0xD SOC29/EOC29/RESULT29 is associated with post processing block 1
0xE SOC30/EOC30/RESULT30 is associated with post processing block 1
0xF SOC31/EOC31/RESULT31 is associated with post processing block 1

Reset type: SYSRSn

24.16.3.60 ADCPPB1STAMP Register (Offset = D6h) [Reset = 0000h]

ADCPPB1STAMP is shown in Figure 24-163 and described in Table 24-141.

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ADC PPB1 Sample Delay Time Stamp Register

Figure 24-163 ADCPPB1STAMP Register
15141312111098
RESERVEDDLYSTAMP
R-0hR-0h
76543210
DLYSTAMP
R-0h
Table 24-141 ADCPPB1STAMP Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0hReserved
11-0DLYSTAMPR0hADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample.

Reset type: SYSRSn

24.16.3.61 ADCPPB1OFFCAL Register (Offset = D8h) [Reset = 0000h]

ADCPPB1OFFCAL is shown in Figure 24-164 and described in Table 24-142.

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ADC PPB1 Offset Calibration Register

Figure 24-164 ADCPPB1OFFCAL Register
15141312111098
RESERVEDOFFCAL
R-0hR/W-0h
76543210
OFFCAL
R/W-0h
Table 24-142 ADCPPB1OFFCAL Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0OFFCALR/W0hADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register.

000h No change. The ADC output is stored directly into ADCRESULT.
001h ADC output - 1 is stored into ADCRESULT.
002h ADC output - 2 is stored into ADCRESULT.
...
200h ADC output + 512 is stored into ADCRESULT.
...
3FFh ADC output + 1 is stored into ADCRESULT.

NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register.

Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied.

Reset type: SYSRSn

24.16.3.62 ADCPPB1OFFREF Register (Offset = DAh) [Reset = 0000h]

ADCPPB1OFFREF is shown in Figure 24-165 and described in Table 24-143.

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ADC PPB1 Offset Reference Register

Figure 24-165 ADCPPB1OFFREF Register
15141312111098
OFFREF
R/W-0h
76543210
OFFREF
R/W-0h
Table 24-143 ADCPPB1OFFREF Register Field Descriptions
BitFieldTypeResetDescription
15-0OFFREFR/W0hADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB1RESULT register. This subtraction is not saturated.

0000h No change. The ADCRESULT value is passed on.
0001h ADCRESULT - 1 is passed on.
0002h ADCRESULT - 2 is passed on.
...
8000h ADCRESULT - 32,768 is passed on.
...
FFFFh ADCRESULT - 65,535 is passed on.

NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode.

Reset type: SYSRSn

24.16.3.63 ADCPPB1TRIPHI Register (Offset = DCh) [Reset = 00000000h]

ADCPPB1TRIPHI is shown in Figure 24-166 and described in Table 24-144.

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ADC PPB1 Trip High Register

Figure 24-166 ADCPPB1TRIPHI Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITHI
R-0hR/W-0h
Table 24-144 ADCPPB1TRIPHI Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0LIMITHIR/W0hADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPHI[23:17] will be ignored in 16 bit mode
- TRIPHI[23:13] will be ignored in 12 bit mode

Reset type: SYSRSn

24.16.3.64 ADCPPB1TRIPLO Register (Offset = E0h) [Reset = 00000000h]

ADCPPB1TRIPLO is shown in Figure 24-167 and described in Table 24-145.

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ADC PPB1 Trip Low/Trigger Time Stamp Register

Figure 24-167 ADCPPB1TRIPLO Register
3130292827262524
REQSTAMP
R-0h
2322212019181716
REQSTAMPLIMITLO2ENRESERVEDLSIGN
R-0hR/W-0hR-0hR/W-0h
15141312111098
LIMITLO
R/W-0h
76543210
LIMITLO
R/W-0h
Table 24-145 ADCPPB1TRIPLO Register Field Descriptions
BitFieldTypeResetDescription
31-20REQSTAMPR0hADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field.

Reset type: SYSRSn

19LIMITLO2ENR/W0hExtended Low Limit 2 Enable.

0 = Low limit set by ADCPPB1TRIPLO register. Not compatible with comparison with ADCPPB1PSUM or ADCPPB1SUM
1 = Low limit set by ADCPPB1TRIPLO2 register

Reset type: SYSRSn

18-17RESERVEDR0hReserved
16LSIGNR/W0hLow Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode.

Reset type: SYSRSn

15-0LIMITLOR/W0hADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB1RESULT register.

Reset type: SYSRSn

24.16.3.65 ADCPPBTRIP1FILCTL Register (Offset = E4h) [Reset = 0000h]

ADCPPBTRIP1FILCTL is shown in Figure 24-168 and described in Table 24-146.

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ADCEVT1 Trip High Filter Control Register

Figure 24-168 ADCPPBTRIP1FILCTL Register
15141312111098
FILINITTHRESHSAMPWIN
R-0/W1S-0hR/W-0hR/W-0h
76543210
SAMPWINRESERVEDFILTLOENFILTHIEN
R/W-0hR-0hR/W-0hR/W-0h
Table 24-146 ADCPPBTRIP1FILCTL Register Field Descriptions
BitFieldTypeResetDescription
15FILINITR-0/W1S0hTrip filter initialization for PPB1.

0 No effect
1 Initialize all samples to the filter input value

This applies to the filter on both the high and low trips.

Reset type: SYSRSn

14-9THRESHR/W0hTrip filter majority voting threshold on PPB1. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. This applies to the filter on both the high and low trips.

Reset type: SYSRSn

8-3SAMPWINR/W0hTrip filter sample window size on PPB1. Number of samples to monitor is SAMPWIN+1. This applies to the filter on both the high and low trips.

Reset type: SYSRSn

2RESERVEDR0hReserved
1FILTLOENR/W0hADC PPB1 TRIPLO Filter Enable

0 No filtering of PPB 1 trip low limit events
1 PPB1 trip high limit event filtering enabled

Reset type: SYSRSn

0FILTHIENR/W0hADC PPB1 TRIPHI Filter Enable

0 No filtering of PPB 1 trip high limit events
1 PPB1 trip high limit event filtering enabled

Reset type: SYSRSn

24.16.3.66 ADCPPBTRIP1FILCLKCTL Register (Offset = E8h) [Reset = 00000000h]

ADCPPBTRIP1FILCLKCTL is shown in Figure 24-169 and described in Table 24-147.

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ADCEVT1 Trip High Filter Prescale Control Register

Figure 24-169 ADCPPBTRIP1FILCLKCTL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLKPRESCALE
R-0hR/W-0h
Table 24-147 ADCPPBTRIP1FILCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CLKPRESCALER/W0hADCPPB1 filter sample clock prescale. The effective prescale value is (CLKPRESCALE + 1). This applies to the filter on both the high and low trips.

Reset type: SYSRSn

24.16.3.67 ADCPPB2CONFIG Register (Offset = F4h) [Reset = 0001h]

ADCPPB2CONFIG is shown in Figure 24-170 and described in Table 24-148.

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ADC PPB{#} Config Register

Figure 24-170 ADCPPB2CONFIG Register
15141312111098
RESERVEDDELTAEN
R-0hR/W-0h
76543210
TWOSCOMPENABSENCBCENCONFIG
R/W-0hR/W-0hR/W-0hR/W-1h
Table 24-148 ADCPPB2CONFIG Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0hReserved
8DELTAENR/W0hADC Post Processing Block 2 enable delta (difference) from last sample calcualtion. When set, the ADCPPB2RESULT register will contain the difference between the most recent conversion result and the last value that would have been loaded into the ADCPPB2RESULT (if the delta calculation wasn't enabled).

The delta calculation occurs after OFFREF, TWOSCOMPEN, and ABSEN calculations are applied.

0 Delta calculation disabled: no modification to ADCPPB2RESULT
1 ADCPPB2RESULT = ADCPPB2RESULT'[t] - ADCPPB2RESULT'[t - 1]

Where ADCPPB2RESULT' is the value that would have been loaded into ADCPPB2RESULT without delta calculation

Reset type: SYSRSn

7TWOSCOMPENR/W0hADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB2RESULT register.

0 ADCPPB2RESULT = ADCRESULTx - ADCPPB2OFFREF
1 ADCPPB2RESULT = ADCPPB2OFFREF - ADCRESULTx

Reset type: SYSRSn

6ABSENR/W0hADC Post Processing Block 2 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB2.

This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT)

0 ADCPPB2RESULT = ADCRESULTx - ADCPPB2OFFREF
1 ADCPPB2RESULT = abs(ADCRESULTx - ADCPPB2OFFREF)

Reset type: SYSRSn

5CBCENR/W0hADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present.

Reset type: SYSRSn

4-0CONFIGR/W1hADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block.

0x0 SOC0/EOC0/RESULT0 is associated with post processing block 2
0x1 SOC1/EOC1/RESULT1 is associated with post processing block 2
0x2 SOC2/EOC2/RESULT2 is associated with post processing block 2
0x3 SOC3/EOC3/RESULT3 is associated with post processing block 2
0x4 SOC4/EOC4/RESULT4 is associated with post processing block 2
0x5 SOC5/EOC5/RESULT5 is associated with post processing block 2
0x6 SOC6/EOC6/RESULT6 is associated with post processing block 2
0x7 SOC7/EOC7/RESULT7 is associated with post processing block 2
0x8 SOC8/EOC8/RESULT8 is associated with post processing block 2
0x9 SOC9/EOC9/RESULT9 is associated with post processing block 2
0xA SOC10/EOC10/RESULT10 is associated with post processing block 2
0xB SOC11/EOC11/RESULT11 is associated with post processing block 2
0xC SOC12/EOC12/RESULT12 is associated with post processing block 2
0xD SOC13/EOC13/RESULT13 is associated with post processing block 2
0xE SOC14/EOC14/RESULT14 is associated with post processing block 2
0xF SOC15/EOC15/RESULT15 is associated with post processing block 2
0x0 SOC16/EOC16/RESULT16 is associated with post processing block 2
0x1 SOC17/EOC17/RESULT17 is associated with post processing block 2
0x2 SOC18/EOC18/RESULT18 is associated with post processing block 2
0x3 SOC19/EOC19/RESULT19 is associated with post processing block 2
0x4 SOC20/EOC20/RESULT20 is associated with post processing block 2
0x5 SOC21/EOC21/RESULT21 is associated with post processing block 2
0x6 SOC22/EOC22/RESULT22 is associated with post processing block 2
0x7 SOC23/EOC23/RESULT23 is associated with post processing block 2
0x8 SOC24/EOC24/RESULT24 is associated with post processing block 2
0x9 SOC25/EOC25/RESULT25 is associated with post processing block 2
0xA SOC26/EOC26/RESULT26 is associated with post processing block 2
0xB SOC27/EOC27/RESULT27 is associated with post processing block 2
0xC SOC28/EOC28/RESULT28 is associated with post processing block 2
0xD SOC29/EOC29/RESULT29 is associated with post processing block 2
0xE SOC30/EOC30/RESULT30 is associated with post processing block 2
0xF SOC31/EOC31/RESULT31 is associated with post processing block 2

Reset type: SYSRSn

24.16.3.68 ADCPPB2STAMP Register (Offset = F6h) [Reset = 0000h]

ADCPPB2STAMP is shown in Figure 24-171 and described in Table 24-149.

Return to the Summary Table.

ADC PPB2 Sample Delay Time Stamp Register

Figure 24-171 ADCPPB2STAMP Register
15141312111098
RESERVEDDLYSTAMP
R-0hR-0h
76543210
DLYSTAMP
R-0h
Table 24-149 ADCPPB2STAMP Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0hReserved
11-0DLYSTAMPR0hADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample.

Reset type: SYSRSn

24.16.3.69 ADCPPB2OFFCAL Register (Offset = F8h) [Reset = 0000h]

ADCPPB2OFFCAL is shown in Figure 24-172 and described in Table 24-150.

Return to the Summary Table.

ADC PPB2 Offset Calibration Register

Figure 24-172 ADCPPB2OFFCAL Register
15141312111098
RESERVEDOFFCAL
R-0hR/W-0h
76543210
OFFCAL
R/W-0h
Table 24-150 ADCPPB2OFFCAL Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0OFFCALR/W0hADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register.

000h No change. The ADC output is stored directly into ADCRESULT.
001h ADC output - 1 is stored into ADCRESULT.
002h ADC output - 2 is stored into ADCRESULT.
...
200h ADC output + 512 is stored into ADCRESULT.
...
3FFh ADC output + 1 is stored into ADCRESULT.

NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register.

Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied.

Reset type: SYSRSn

24.16.3.70 ADCPPB2OFFREF Register (Offset = FAh) [Reset = 0000h]

ADCPPB2OFFREF is shown in Figure 24-173 and described in Table 24-151.

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ADC PPB2 Offset Reference Register

Figure 24-173 ADCPPB2OFFREF Register
15141312111098
OFFREF
R/W-0h
76543210
OFFREF
R/W-0h
Table 24-151 ADCPPB2OFFREF Register Field Descriptions
BitFieldTypeResetDescription
15-0OFFREFR/W0hADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB2RESULT register. This subtraction is not saturated.

0000h No change. The ADCRESULT value is passed on.
0001h ADCRESULT - 1 is passed on.
0002h ADCRESULT - 2 is passed on.
...
8000h ADCRESULT - 32,768 is passed on.
...
FFFFh ADCRESULT - 65,535 is passed on.

NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode.

Reset type: SYSRSn

24.16.3.71 ADCPPB2TRIPHI Register (Offset = FCh) [Reset = 00000000h]

ADCPPB2TRIPHI is shown in Figure 24-174 and described in Table 24-152.

Return to the Summary Table.

ADC PPB2 Trip High Register

Figure 24-174 ADCPPB2TRIPHI Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITHI
R-0hR/W-0h
Table 24-152 ADCPPB2TRIPHI Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0LIMITHIR/W0hADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPHI[23:17] will be ignored in 16 bit mode
- TRIPHI[23:13] will be ignored in 12 bit mode

Reset type: SYSRSn

24.16.3.72 ADCPPB2TRIPLO Register (Offset = 100h) [Reset = 00000000h]

ADCPPB2TRIPLO is shown in Figure 24-175 and described in Table 24-153.

Return to the Summary Table.

ADC PPB2 Trip Low/Trigger Time Stamp Register

Figure 24-175 ADCPPB2TRIPLO Register
3130292827262524
REQSTAMP
R-0h
2322212019181716
REQSTAMPLIMITLO2ENRESERVEDLSIGN
R-0hR/W-0hR-0hR/W-0h
15141312111098
LIMITLO
R/W-0h
76543210
LIMITLO
R/W-0h
Table 24-153 ADCPPB2TRIPLO Register Field Descriptions
BitFieldTypeResetDescription
31-20REQSTAMPR0hADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field.

Reset type: SYSRSn

19LIMITLO2ENR/W0hExtended Low Limit 2 Enable.

0 = Low limit set by ADCPPB2TRIPLO register. Not compatible with comparison with ADCPPB2PSUM or ADCPPB2SUM
1 = Low limit set by ADCPPB2TRIPLO2 register

Reset type: SYSRSn

18-17RESERVEDR0hReserved
16LSIGNR/W0hLow Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode.

Reset type: SYSRSn

15-0LIMITLOR/W0hADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB2RESULT register.

Reset type: SYSRSn

24.16.3.73 ADCPPBTRIP2FILCTL Register (Offset = 104h) [Reset = 0000h]

ADCPPBTRIP2FILCTL is shown in Figure 24-176 and described in Table 24-154.

Return to the Summary Table.

ADCEVT2 Trip High Filter Control Register

Figure 24-176 ADCPPBTRIP2FILCTL Register
15141312111098
FILINITTHRESHSAMPWIN
R-0/W1S-0hR/W-0hR/W-0h
76543210
SAMPWINRESERVEDFILTLOENFILTHIEN
R/W-0hR-0hR/W-0hR/W-0h
Table 24-154 ADCPPBTRIP2FILCTL Register Field Descriptions
BitFieldTypeResetDescription
15FILINITR-0/W1S0hTrip filter initialization for PPB2.

0 No effect
1 Initialize all samples to the filter input value

This applies to the filter on both the high and low trips.

Reset type: SYSRSn

14-9THRESHR/W0hTrip filter majority voting threshold on PPB2. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. This applies to the filter on both the high and low trips.

Reset type: SYSRSn

8-3SAMPWINR/W0hTrip filter sample window size on PPB2. Number of samples to monitor is SAMPWIN+1. This applies to the filter on both the high and low trips.

Reset type: SYSRSn

2RESERVEDR0hReserved
1FILTLOENR/W0hADC PPB2 TRIPLO Filter Enable

0 No filtering of PPB 2 trip low limit events
1 PPB2 trip high limit event filtering enabled

Reset type: SYSRSn

0FILTHIENR/W0hADC PPB2 TRIPHI Filter Enable

0 No filtering of PPB 2 trip high limit events
1 PPB2 trip high limit event filtering enabled

Reset type: SYSRSn

24.16.3.74 ADCPPBTRIP2FILCLKCTL Register (Offset = 108h) [Reset = 00000000h]

ADCPPBTRIP2FILCLKCTL is shown in Figure 24-177 and described in Table 24-155.

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ADCEVT2 Trip High Filter Prescale Control Register

Figure 24-177 ADCPPBTRIP2FILCLKCTL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLKPRESCALE
R-0hR/W-0h
Table 24-155 ADCPPBTRIP2FILCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CLKPRESCALER/W0hADCPPB2 filter sample clock prescale. The effective prescale value is (CLKPRESCALE + 1). This applies to the filter on both the high and low trips.

Reset type: SYSRSn

24.16.3.75 ADCPPB3CONFIG Register (Offset = 114h) [Reset = 0002h]

ADCPPB3CONFIG is shown in Figure 24-178 and described in Table 24-156.

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ADC PPB{#} Config Register

Figure 24-178 ADCPPB3CONFIG Register
15141312111098
RESERVEDDELTAEN
R-0hR/W-0h
76543210
TWOSCOMPENABSENCBCENCONFIG
R/W-0hR/W-0hR/W-0hR/W-2h
Table 24-156 ADCPPB3CONFIG Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0hReserved
8DELTAENR/W0hADC Post Processing Block 3 enable delta (difference) from last sample calcualtion. When set, the ADCPPB3RESULT register will contain the difference between the most recent conversion result and the last value that would have been loaded into the ADCPPB3RESULT (if the delta calculation wasn't enabled).

The delta calculation occurs after OFFREF, TWOSCOMPEN, and ABSEN calculations are applied.

0 Delta calculation disabled: no modification to ADCPPB3RESULT
1 ADCPPB3RESULT = ADCPPB3RESULT'[t] - ADCPPB3RESULT'[t - 1]

Where ADCPPB3RESULT' is the value that would have been loaded into ADCPPB3RESULT without delta calculation

Reset type: SYSRSn

7TWOSCOMPENR/W0hADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB3RESULT register.

0 ADCPPB3RESULT = ADCRESULTx - ADCPPB3OFFREF
1 ADCPPB3RESULT = ADCPPB3OFFREF - ADCRESULTx

Reset type: SYSRSn

6ABSENR/W0hADC Post Processing Block 3 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB3.

This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT)

0 ADCPPB3RESULT = ADCRESULTx - ADCPPB3OFFREF
1 ADCPPB3RESULT = abs(ADCRESULTx - ADCPPB3OFFREF)

Reset type: SYSRSn

5CBCENR/W0hADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present.

Reset type: SYSRSn

4-0CONFIGR/W2hADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block.

0x0 SOC0/EOC0/RESULT0 is associated with post processing block 3
0x1 SOC1/EOC1/RESULT1 is associated with post processing block 3
0x2 SOC2/EOC2/RESULT2 is associated with post processing block 3
0x3 SOC3/EOC3/RESULT3 is associated with post processing block 3
0x4 SOC4/EOC4/RESULT4 is associated with post processing block 3
0x5 SOC5/EOC5/RESULT5 is associated with post processing block 3
0x6 SOC6/EOC6/RESULT6 is associated with post processing block 3
0x7 SOC7/EOC7/RESULT7 is associated with post processing block 3
0x8 SOC8/EOC8/RESULT8 is associated with post processing block 3
0x9 SOC9/EOC9/RESULT9 is associated with post processing block 3
0xA SOC10/EOC10/RESULT10 is associated with post processing block 3
0xB SOC11/EOC11/RESULT11 is associated with post processing block 3
0xC SOC12/EOC12/RESULT12 is associated with post processing block 3
0xD SOC13/EOC13/RESULT13 is associated with post processing block 3
0xE SOC14/EOC14/RESULT14 is associated with post processing block 3
0xF SOC15/EOC15/RESULT15 is associated with post processing block 3
0x0 SOC16/EOC16/RESULT16 is associated with post processing block 3
0x1 SOC17/EOC17/RESULT17 is associated with post processing block 3
0x2 SOC18/EOC18/RESULT18 is associated with post processing block 3
0x3 SOC19/EOC19/RESULT19 is associated with post processing block 3
0x4 SOC20/EOC20/RESULT20 is associated with post processing block 3
0x5 SOC21/EOC21/RESULT21 is associated with post processing block 3
0x6 SOC22/EOC22/RESULT22 is associated with post processing block 3
0x7 SOC23/EOC23/RESULT23 is associated with post processing block 3
0x8 SOC24/EOC24/RESULT24 is associated with post processing block 3
0x9 SOC25/EOC25/RESULT25 is associated with post processing block 3
0xA SOC26/EOC26/RESULT26 is associated with post processing block 3
0xB SOC27/EOC27/RESULT27 is associated with post processing block 3
0xC SOC28/EOC28/RESULT28 is associated with post processing block 3
0xD SOC29/EOC29/RESULT29 is associated with post processing block 3
0xE SOC30/EOC30/RESULT30 is associated with post processing block 3
0xF SOC31/EOC31/RESULT31 is associated with post processing block 3

Reset type: SYSRSn

24.16.3.76 ADCPPB3STAMP Register (Offset = 116h) [Reset = 0000h]

ADCPPB3STAMP is shown in Figure 24-179 and described in Table 24-157.

Return to the Summary Table.

ADC PPB3 Sample Delay Time Stamp Register

Figure 24-179 ADCPPB3STAMP Register
15141312111098
RESERVEDDLYSTAMP
R-0hR-0h
76543210
DLYSTAMP
R-0h
Table 24-157 ADCPPB3STAMP Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0hReserved
11-0DLYSTAMPR0hADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample.

Reset type: SYSRSn

24.16.3.77 ADCPPB3OFFCAL Register (Offset = 118h) [Reset = 0000h]

ADCPPB3OFFCAL is shown in Figure 24-180 and described in Table 24-158.

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ADC PPB3 Offset Calibration Register

Figure 24-180 ADCPPB3OFFCAL Register
15141312111098
RESERVEDOFFCAL
R-0hR/W-0h
76543210
OFFCAL
R/W-0h
Table 24-158 ADCPPB3OFFCAL Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0OFFCALR/W0hADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register.

000h No change. The ADC output is stored directly into ADCRESULT.
001h ADC output - 1 is stored into ADCRESULT.
002h ADC output - 2 is stored into ADCRESULT.
...
200h ADC output + 512 is stored into ADCRESULT.
...
3FFh ADC output + 1 is stored into ADCRESULT.

NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register.

Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied.

Reset type: SYSRSn

24.16.3.78 ADCPPB3OFFREF Register (Offset = 11Ah) [Reset = 0000h]

ADCPPB3OFFREF is shown in Figure 24-181 and described in Table 24-159.

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ADC PPB3 Offset Reference Register

Figure 24-181 ADCPPB3OFFREF Register
15141312111098
OFFREF
R/W-0h
76543210
OFFREF
R/W-0h
Table 24-159 ADCPPB3OFFREF Register Field Descriptions
BitFieldTypeResetDescription
15-0OFFREFR/W0hADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB3RESULT register. This subtraction is not saturated.

0000h No change. The ADCRESULT value is passed on.
0001h ADCRESULT - 1 is passed on.
0002h ADCRESULT - 2 is passed on.
...
8000h ADCRESULT - 32,768 is passed on.
...
FFFFh ADCRESULT - 65,535 is passed on.

NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode.

Reset type: SYSRSn

24.16.3.79 ADCPPB3TRIPHI Register (Offset = 11Ch) [Reset = 00000000h]

ADCPPB3TRIPHI is shown in Figure 24-182 and described in Table 24-160.

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ADC PPB3 Trip High Register

Figure 24-182 ADCPPB3TRIPHI Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITHI
R-0hR/W-0h
Table 24-160 ADCPPB3TRIPHI Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0LIMITHIR/W0hADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPHI[23:17] will be ignored in 16 bit mode
- TRIPHI[23:13] will be ignored in 12 bit mode

Reset type: SYSRSn

24.16.3.80 ADCPPB3TRIPLO Register (Offset = 120h) [Reset = 00000000h]

ADCPPB3TRIPLO is shown in Figure 24-183 and described in Table 24-161.

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ADC PPB3 Trip Low/Trigger Time Stamp Register

Figure 24-183 ADCPPB3TRIPLO Register
3130292827262524
REQSTAMP
R-0h
2322212019181716
REQSTAMPLIMITLO2ENRESERVEDLSIGN
R-0hR/W-0hR-0hR/W-0h
15141312111098
LIMITLO
R/W-0h
76543210
LIMITLO
R/W-0h
Table 24-161 ADCPPB3TRIPLO Register Field Descriptions
BitFieldTypeResetDescription
31-20REQSTAMPR0hADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field.

Reset type: SYSRSn

19LIMITLO2ENR/W0hExtended Low Limit 2 Enable.

0 = Low limit set by ADCPPB3TRIPLO register. Not compatible with comparison with ADCPPB3PSUM or ADCPPB3SUM
1 = Low limit set by ADCPPB3TRIPLO2 register

Reset type: SYSRSn

18-17RESERVEDR0hReserved
16LSIGNR/W0hLow Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode.

Reset type: SYSRSn

15-0LIMITLOR/W0hADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB3RESULT register.

Reset type: SYSRSn

24.16.3.81 ADCPPBTRIP3FILCTL Register (Offset = 124h) [Reset = 0000h]

ADCPPBTRIP3FILCTL is shown in Figure 24-184 and described in Table 24-162.

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ADCEVT3 Trip High Filter Control Register

Figure 24-184 ADCPPBTRIP3FILCTL Register
15141312111098
FILINITTHRESHSAMPWIN
R-0/W1S-0hR/W-0hR/W-0h
76543210
SAMPWINRESERVEDFILTLOENFILTHIEN
R/W-0hR-0hR/W-0hR/W-0h
Table 24-162 ADCPPBTRIP3FILCTL Register Field Descriptions
BitFieldTypeResetDescription
15FILINITR-0/W1S0hTrip filter initialization for PPB3.

0 No effect
1 Initialize all samples to the filter input value

This applies to the filter on both the high and low trips.

Reset type: SYSRSn

14-9THRESHR/W0hTrip filter majority voting threshold on PPB3. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. This applies to the filter on both the high and low trips.

Reset type: SYSRSn

8-3SAMPWINR/W0hTrip filter sample window size on PPB3. Number of samples to monitor is SAMPWIN+1. This applies to the filter on both the high and low trips.

Reset type: SYSRSn

2RESERVEDR0hReserved
1FILTLOENR/W0hADC PPB3 TRIPLO Filter Enable

0 No filtering of PPB 3 trip low limit events
1 PPB3 trip high limit event filtering enabled

Reset type: SYSRSn

0FILTHIENR/W0hADC PPB3 TRIPHI Filter Enable

0 No filtering of PPB 3 trip high limit events
1 PPB3 trip high limit event filtering enabled

Reset type: SYSRSn

24.16.3.82 ADCPPBTRIP3FILCLKCTL Register (Offset = 128h) [Reset = 00000000h]

ADCPPBTRIP3FILCLKCTL is shown in Figure 24-185 and described in Table 24-163.

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ADCEVT3 Trip High Filter Prescale Control Register

Figure 24-185 ADCPPBTRIP3FILCLKCTL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLKPRESCALE
R-0hR/W-0h
Table 24-163 ADCPPBTRIP3FILCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CLKPRESCALER/W0hADCPPB3 filter sample clock prescale. The effective prescale value is (CLKPRESCALE + 1). This applies to the filter on both the high and low trips.

Reset type: SYSRSn

24.16.3.83 ADCPPB4CONFIG Register (Offset = 134h) [Reset = 0003h]

ADCPPB4CONFIG is shown in Figure 24-186 and described in Table 24-164.

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ADC PPB{#} Config Register

Figure 24-186 ADCPPB4CONFIG Register
15141312111098
RESERVEDDELTAEN
R-0hR/W-0h
76543210
TWOSCOMPENABSENCBCENCONFIG
R/W-0hR/W-0hR/W-0hR/W-3h
Table 24-164 ADCPPB4CONFIG Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR0hReserved
8DELTAENR/W0hADC Post Processing Block 4 enable delta (difference) from last sample calcualtion. When set, the ADCPPB4RESULT register will contain the difference between the most recent conversion result and the last value that would have been loaded into the ADCPPB4RESULT (if the delta calculation wasn't enabled).

The delta calculation occurs after OFFREF, TWOSCOMPEN, and ABSEN calculations are applied.

0 Delta calculation disabled: no modification to ADCPPB4RESULT
1 ADCPPB4RESULT = ADCPPB4RESULT'[t] - ADCPPB4RESULT'[t - 1]

Where ADCPPB4RESULT' is the value that would have been loaded into ADCPPB4RESULT without delta calculation

Reset type: SYSRSn

7TWOSCOMPENR/W0hADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in the ADCPPB4RESULT register.

0 ADCPPB4RESULT = ADCRESULTx - ADCPPB4OFFREF
1 ADCPPB4RESULT = ADCPPB4OFFREF - ADCRESULTx

Reset type: SYSRSn

6ABSENR/W0hADC Post Processing Block 4 Absolute Value Enable. When set this bit enables absolute value calculation on the ADCRESULx associated with ADCPPB4.

This occurs before the TWOSCOMPEN logic is evaluated (so enabling both TWOSCOMPEN and ABSEN will always result in a negative value stored in ADCPPBxRESULT)

0 ADCPPB4RESULT = ADCRESULTx - ADCPPB4OFFREF
1 ADCPPB4RESULT = abs(ADCRESULTx - ADCPPB4OFFREF)

Reset type: SYSRSn

5CBCENR/W0hADC Post Processing Block Cycle By Cycle Enable. When set, this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present.

Reset type: SYSRSn

4-0CONFIGR/W3hADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block.

0x0 SOC0/EOC0/RESULT0 is associated with post processing block 4
0x1 SOC1/EOC1/RESULT1 is associated with post processing block 4
0x2 SOC2/EOC2/RESULT2 is associated with post processing block 4
0x3 SOC3/EOC3/RESULT3 is associated with post processing block 4
0x4 SOC4/EOC4/RESULT4 is associated with post processing block 4
0x5 SOC5/EOC5/RESULT5 is associated with post processing block 4
0x6 SOC6/EOC6/RESULT6 is associated with post processing block 4
0x7 SOC7/EOC7/RESULT7 is associated with post processing block 4
0x8 SOC8/EOC8/RESULT8 is associated with post processing block 4
0x9 SOC9/EOC9/RESULT9 is associated with post processing block 4
0xA SOC10/EOC10/RESULT10 is associated with post processing block 4
0xB SOC11/EOC11/RESULT11 is associated with post processing block 4
0xC SOC12/EOC12/RESULT12 is associated with post processing block 4
0xD SOC13/EOC13/RESULT13 is associated with post processing block 4
0xE SOC14/EOC14/RESULT14 is associated with post processing block 4
0xF SOC15/EOC15/RESULT15 is associated with post processing block 4
0x0 SOC16/EOC16/RESULT16 is associated with post processing block 4
0x1 SOC17/EOC17/RESULT17 is associated with post processing block 4
0x2 SOC18/EOC18/RESULT18 is associated with post processing block 4
0x3 SOC19/EOC19/RESULT19 is associated with post processing block 4
0x4 SOC20/EOC20/RESULT20 is associated with post processing block 4
0x5 SOC21/EOC21/RESULT21 is associated with post processing block 4
0x6 SOC22/EOC22/RESULT22 is associated with post processing block 4
0x7 SOC23/EOC23/RESULT23 is associated with post processing block 4
0x8 SOC24/EOC24/RESULT24 is associated with post processing block 4
0x9 SOC25/EOC25/RESULT25 is associated with post processing block 4
0xA SOC26/EOC26/RESULT26 is associated with post processing block 4
0xB SOC27/EOC27/RESULT27 is associated with post processing block 4
0xC SOC28/EOC28/RESULT28 is associated with post processing block 4
0xD SOC29/EOC29/RESULT29 is associated with post processing block 4
0xE SOC30/EOC30/RESULT30 is associated with post processing block 4
0xF SOC31/EOC31/RESULT31 is associated with post processing block 4

Reset type: SYSRSn

24.16.3.84 ADCPPB4STAMP Register (Offset = 136h) [Reset = 0000h]

ADCPPB4STAMP is shown in Figure 24-187 and described in Table 24-165.

Return to the Summary Table.

ADC PPB4 Sample Delay Time Stamp Register

Figure 24-187 ADCPPB4STAMP Register
15141312111098
RESERVEDDLYSTAMP
R-0hR-0h
76543210
DLYSTAMP
R-0h
Table 24-165 ADCPPB4STAMP Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0hReserved
11-0DLYSTAMPR0hADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field, thereby giving the number of system clock cycles delay between the SOC trigger and the actual start of the sample.

Reset type: SYSRSn

24.16.3.85 ADCPPB4OFFCAL Register (Offset = 138h) [Reset = 0000h]

ADCPPB4OFFCAL is shown in Figure 24-188 and described in Table 24-166.

Return to the Summary Table.

ADC PPB4 Offset Calibration Register

Figure 24-188 ADCPPB4OFFCAL Register
15141312111098
RESERVEDOFFCAL
R-0hR/W-0h
76543210
OFFCAL
R/W-0h
Table 24-166 ADCPPB4OFFCAL Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0OFFCALR/W0hADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT register.

000h No change. The ADC output is stored directly into ADCRESULT.
001h ADC output - 1 is stored into ADCRESULT.
002h ADC output - 2 is stored into ADCRESULT.
...
200h ADC output + 512 is stored into ADCRESULT.
...
3FFh ADC output + 1 is stored into ADCRESULT.

NOTE: In 16-bit mode, the subtraction will saturate at 0000h and FFFFh before being stored into the ADCRESULT register. In 12-bit mode, the subtraction will saturate at 0000h and 0FFFh before being stored into the ADCRESULT register.

Note: in the case that multiple PPBs point to the same SOC, only the OFFCAL of the lowest numbered PPB will be applied.

Reset type: SYSRSn

24.16.3.86 ADCPPB4OFFREF Register (Offset = 13Ah) [Reset = 0000h]

ADCPPB4OFFREF is shown in Figure 24-189 and described in Table 24-167.

Return to the Summary Table.

ADC PPB4 Offset Reference Register

Figure 24-189 ADCPPB4OFFREF Register
15141312111098
OFFREF
R/W-0h
76543210
OFFREF
R/W-0h
Table 24-167 ADCPPB4OFFREF Register Field Descriptions
BitFieldTypeResetDescription
15-0OFFREFR/W0hADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT register before being passed through an optional two's complement function and stored in the ADCPPB4RESULT register. This subtraction is not saturated.

0000h No change. The ADCRESULT value is passed on.
0001h ADCRESULT - 1 is passed on.
0002h ADCRESULT - 2 is passed on.
...
8000h ADCRESULT - 32,768 is passed on.
...
FFFFh ADCRESULT - 65,535 is passed on.

NOTE: In 12-bit mode the size of this register does not change from 16-bits. It is the user's responsibility to ensure that only a 12-bit value is written to this register when in 12-bit mode.

Reset type: SYSRSn

24.16.3.87 ADCPPB4TRIPHI Register (Offset = 13Ch) [Reset = 00000000h]

ADCPPB4TRIPHI is shown in Figure 24-190 and described in Table 24-168.

Return to the Summary Table.

ADC PPB4 Trip High Register

Figure 24-190 ADCPPB4TRIPHI Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITHI
R-0hR/W-0h
Table 24-168 ADCPPB4TRIPHI Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0LIMITHIR/W0hADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPHI[23:17] will be ignored in 16 bit mode
- TRIPHI[23:13] will be ignored in 12 bit mode

Reset type: SYSRSn

24.16.3.88 ADCPPB4TRIPLO Register (Offset = 140h) [Reset = 00000000h]

ADCPPB4TRIPLO is shown in Figure 24-191 and described in Table 24-169.

Return to the Summary Table.

ADC PPB4 Trip Low/Trigger Time Stamp Register

Figure 24-191 ADCPPB4TRIPLO Register
3130292827262524
REQSTAMP
R-0h
2322212019181716
REQSTAMPLIMITLO2ENRESERVEDLSIGN
R-0hR/W-0hR-0hR/W-0h
15141312111098
LIMITLO
R/W-0h
76543210
LIMITLO
R/W-0h
Table 24-169 ADCPPB4TRIPLO Register Field Descriptions
BitFieldTypeResetDescription
31-20REQSTAMPR0hADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field.

Reset type: SYSRSn

19LIMITLO2ENR/W0hExtended Low Limit 2 Enable.

0 = Low limit set by ADCPPB4TRIPLO register. Not compatible with comparison with ADCPPB4PSUM or ADCPPB4SUM
1 = Low limit set by ADCPPB4TRIPLO2 register

Reset type: SYSRSn

18-17RESERVEDR0hReserved
16LSIGNR/W0hLow Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode.

Reset type: SYSRSn

15-0LIMITLOR/W0hADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0 will be compared against bits 12:0 of the PPBRSULT bit field of the ADCPPB4RESULT register.

Reset type: SYSRSn

24.16.3.89 ADCPPBTRIP4FILCTL Register (Offset = 144h) [Reset = 0000h]

ADCPPBTRIP4FILCTL is shown in Figure 24-192 and described in Table 24-170.

Return to the Summary Table.

ADCEVT4 Trip High Filter Control Register

Figure 24-192 ADCPPBTRIP4FILCTL Register
15141312111098
FILINITTHRESHSAMPWIN
R-0/W1S-0hR/W-0hR/W-0h
76543210
SAMPWINRESERVEDFILTLOENFILTHIEN
R/W-0hR-0hR/W-0hR/W-0h
Table 24-170 ADCPPBTRIP4FILCTL Register Field Descriptions
BitFieldTypeResetDescription
15FILINITR-0/W1S0hTrip filter initialization for PPB4.

0 No effect
1 Initialize all samples to the filter input value

This applies to the filter on both the high and low trips.

Reset type: SYSRSn

14-9THRESHR/W0hTrip filter majority voting threshold on PPB4. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1. This applies to the filter on both the high and low trips.

Reset type: SYSRSn

8-3SAMPWINR/W0hTrip filter sample window size on PPB4. Number of samples to monitor is SAMPWIN+1. This applies to the filter on both the high and low trips.

Reset type: SYSRSn

2RESERVEDR0hReserved
1FILTLOENR/W0hADC PPB4 TRIPLO Filter Enable

0 No filtering of PPB 4 trip low limit events
1 PPB4 trip high limit event filtering enabled

Reset type: SYSRSn

0FILTHIENR/W0hADC PPB4 TRIPHI Filter Enable

0 No filtering of PPB 4 trip high limit events
1 PPB4 trip high limit event filtering enabled

Reset type: SYSRSn

24.16.3.90 ADCPPBTRIP4FILCLKCTL Register (Offset = 148h) [Reset = 00000000h]

ADCPPBTRIP4FILCLKCTL is shown in Figure 24-193 and described in Table 24-171.

Return to the Summary Table.

ADCEVT4 Trip High Filter Prescale Control Register

Figure 24-193 ADCPPBTRIP4FILCLKCTL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLKPRESCALE
R-0hR/W-0h
Table 24-171 ADCPPBTRIP4FILCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CLKPRESCALER/W0hADCPPB4 filter sample clock prescale. The effective prescale value is (CLKPRESCALE + 1). This applies to the filter on both the high and low trips.

Reset type: SYSRSn

24.16.3.91 ADCSAFECHECKRESEN Register (Offset = 154h) [Reset = 00000000h]

ADCSAFECHECKRESEN is shown in Figure 24-194 and described in Table 24-172.

Return to the Summary Table.

ADC Safe Check Result Enable Register

Figure 24-194 ADCSAFECHECKRESEN Register
3130292827262524
SOC15CHKENSOC14CHKENSOC13CHKENSOC12CHKEN
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
SOC11CHKENSOC10CHKENSOC9CHKENSOC8CHKEN
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
SOC7CHKENSOC6CHKENSOC5CHKENSOC4CHKEN
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
SOC3CHKENSOC2CHKENSOC1CHKENSOC0CHKEN
R/W-0hR/W-0hR/W-0hR/W-0h
Table 24-172 ADCSAFECHECKRESEN Register Field Descriptions
BitFieldTypeResetDescription
31-30SOC15CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT15 passed to safety checker
10 PPB Result associated with SOC15 passed to safety checker
11 PPB Sum associated with SOC15 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

29-28SOC14CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT14 passed to safety checker
10 PPB Result associated with SOC14 passed to safety checker
11 PPB Sum associated with SOC14 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

27-26SOC13CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT13 passed to safety checker
10 PPB Result associated with SOC13 passed to safety checker
11 PPB Sum associated with SOC13 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

25-24SOC12CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT12 passed to safety checker
10 PPB Result associated with SOC12 passed to safety checker
11 PPB Sum associated with SOC12 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

23-22SOC11CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT11 passed to safety checker
10 PPB Result associated with SOC11 passed to safety checker
11 PPB Sum associated with SOC11 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

21-20SOC10CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT10 passed to safety checker
10 PPB Result associated with SOC10 passed to safety checker
11 PPB Sum associated with SOC10 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

19-18SOC9CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT9 passed to safety checker
10 PPB Result associated with SOC9 passed to safety checker
11 PPB Sum associated with SOC9 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

17-16SOC8CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT8 passed to safety checker
10 PPB Result associated with SOC8 passed to safety checker
11 PPB Sum associated with SOC8 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

15-14SOC7CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT7 passed to safety checker
10 PPB Result associated with SOC7 passed to safety checker
11 PPB Sum associated with SOC7 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

13-12SOC6CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT6 passed to safety checker
10 PPB Result associated with SOC6 passed to safety checker
11 PPB Sum associated with SOC6 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

11-10SOC5CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT5 passed to safety checker
10 PPB Result associated with SOC5 passed to safety checker
11 PPB Sum associated with SOC5 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

9-8SOC4CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT4 passed to safety checker
10 PPB Result associated with SOC4 passed to safety checker
11 PPB Sum associated with SOC4 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

7-6SOC3CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT3 passed to safety checker
10 PPB Result associated with SOC3 passed to safety checker
11 PPB Sum associated with SOC3 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

5-4SOC2CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT2 passed to safety checker
10 PPB Result associated with SOC2 passed to safety checker
11 PPB Sum associated with SOC2 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

3-2SOC1CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT1 passed to safety checker
10 PPB Result associated with SOC1 passed to safety checker
11 PPB Sum associated with SOC1 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

1-0SOC0CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT0 passed to safety checker
10 PPB Result associated with SOC0 passed to safety checker
11 PPB Sum associated with SOC0 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

24.16.3.92 ADCSAFECHECKRESEN2 Register (Offset = 158h) [Reset = 00000000h]

ADCSAFECHECKRESEN2 is shown in Figure 24-195 and described in Table 24-173.

Return to the Summary Table.

ADC Safe Check Result Enable 2 Register

Figure 24-195 ADCSAFECHECKRESEN2 Register
3130292827262524
SOC31CHKENSOC30CHKENSOC29CHKENSOC28CHKEN
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
SOC27CHKENSOC26CHKENSOC25CHKENSOC24CHKEN
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
SOC23CHKENSOC22CHKENSOC21CHKENSOC20CHKEN
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
SOC19CHKENSOC18CHKENSOC17CHKENSOC16CHKEN
R/W-0hR/W-0hR/W-0hR/W-0h
Table 24-173 ADCSAFECHECKRESEN2 Register Field Descriptions
BitFieldTypeResetDescription
31-30SOC31CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT31 passed to safety checker
10 PPB Result associated with SOC31 passed to safety checker
11 PPB Sum associated with SOC31 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

29-28SOC30CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT30 passed to safety checker
10 PPB Result associated with SOC30 passed to safety checker
11 PPB Sum associated with SOC30 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

27-26SOC29CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT29 passed to safety checker
10 PPB Result associated with SOC29 passed to safety checker
11 PPB Sum associated with SOC29 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

25-24SOC28CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT28 passed to safety checker
10 PPB Result associated with SOC28 passed to safety checker
11 PPB Sum associated with SOC28 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

23-22SOC27CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT27 passed to safety checker
10 PPB Result associated with SOC27 passed to safety checker
11 PPB Sum associated with SOC27 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

21-20SOC26CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT26 passed to safety checker
10 PPB Result associated with SOC26 passed to safety checker
11 PPB Sum associated with SOC26 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

19-18SOC25CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT25 passed to safety checker
10 PPB Result associated with SOC25 passed to safety checker
11 PPB Sum associated with SOC25 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

17-16SOC24CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT24 passed to safety checker
10 PPB Result associated with SOC24 passed to safety checker
11 PPB Sum associated with SOC24 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

15-14SOC23CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT23 passed to safety checker
10 PPB Result associated with SOC23 passed to safety checker
11 PPB Sum associated with SOC23 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

13-12SOC22CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT22 passed to safety checker
10 PPB Result associated with SOC22 passed to safety checker
11 PPB Sum associated with SOC22 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

11-10SOC21CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT21 passed to safety checker
10 PPB Result associated with SOC21 passed to safety checker
11 PPB Sum associated with SOC21 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

9-8SOC20CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT20 passed to safety checker
10 PPB Result associated with SOC20 passed to safety checker
11 PPB Sum associated with SOC20 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

7-6SOC19CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT19 passed to safety checker
10 PPB Result associated with SOC19 passed to safety checker
11 PPB Sum associated with SOC19 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

5-4SOC18CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT18 passed to safety checker
10 PPB Result associated with SOC18 passed to safety checker
11 PPB Sum associated with SOC18 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

3-2SOC17CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT17 passed to safety checker
10 PPB Result associated with SOC17 passed to safety checker
11 PPB Sum associated with SOC17 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

1-0SOC16CHKENR/W0hDetermine which result will be passed to the safety result checker. Only one of the raw ADC result, the PPB result, or the final PPB accumulated SUM can be passed on to the checker for each conversion.

00 No result passed to safety checker
01 ADCRESULT16 passed to safety checker
10 PPB Result associated with SOC16 passed to safety checker
11 PPB Sum associated with SOC16 passed to safety chekcer

Note: if multiple PPBs point to the same SOC, the lowest numbered PPB will have priority to pass its result to the safety checker

Reset type: SYSRSn

24.16.3.93 ADCINTCYCLE Register (Offset = 172h) [Reset = 0000h]

ADCINTCYCLE is shown in Figure 24-196 and described in Table 24-174.

Return to the Summary Table.

ADC Early Interrupt Generation Cycle

Figure 24-196 ADCINTCYCLE Register
15141312111098
DELAY
R/W-0h
76543210
DELAY
R/W-0h
Table 24-174 ADCINTCYCLE Register Field Descriptions
BitFieldTypeResetDescription
15-0DELAYR/W0hADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles, for the interrupt to be generated.

Reset type: SYSRSn

24.16.3.94 ADCINLTRIM1 Register (Offset = 174h) [Reset = X0000000h]

ADCINLTRIM1 is shown in Figure 24-197 and described in Table 24-175.

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ADC Linearity Trim 1 Register

Figure 24-197 ADCINLTRIM1 Register
313029282726252423222120191817161514131211109876543210
INLTRIM31TO0
R/W-Xh
Table 24-175 ADCINLTRIM1 Register Field Descriptions
BitFieldTypeResetDescription
31-0INLTRIM31TO0R/WXhADC Linearity Trim Bits 31-0.

This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications.

Reset type: XRSn

24.16.3.95 ADCINLTRIM2 Register (Offset = 178h) [Reset = X0000000h]

ADCINLTRIM2 is shown in Figure 24-198 and described in Table 24-176.

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ADC Linearity Trim 2 Register

Figure 24-198 ADCINLTRIM2 Register
313029282726252423222120191817161514131211109876543210
INLTRIM63TO32
R/W-Xh
Table 24-176 ADCINLTRIM2 Register Field Descriptions
BitFieldTypeResetDescription
31-0INLTRIM63TO32R/WXhADC Linearity Trim Bits 63-32.

This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications.

Reset type: XRSn

24.16.3.96 ADCINLTRIM3 Register (Offset = 17Ch) [Reset = X0000000h]

ADCINLTRIM3 is shown in Figure 24-199 and described in Table 24-177.

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ADC Linearity Trim 3 Register

Figure 24-199 ADCINLTRIM3 Register
313029282726252423222120191817161514131211109876543210
INLTRIM95TO64
R/W-Xh
Table 24-177 ADCINLTRIM3 Register Field Descriptions
BitFieldTypeResetDescription
31-0INLTRIM95TO64R/WXhADC Linearity Trim Bits 95-64.

This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications.

Reset type: XRSn

24.16.3.97 ADCINLTRIM4 Register (Offset = 180h) [Reset = X0000000h]

ADCINLTRIM4 is shown in Figure 24-200 and described in Table 24-178.

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ADC Linearity Trim 4 Register

Figure 24-200 ADCINLTRIM4 Register
313029282726252423222120191817161514131211109876543210
INLTRIM127TO96
R/W-Xh
Table 24-178 ADCINLTRIM4 Register Field Descriptions
BitFieldTypeResetDescription
31-0INLTRIM127TO96R/WXhADC Linearity Trim Bits 127-96.

This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications.

Reset type: XRSn

24.16.3.98 ADCINLTRIM5 Register (Offset = 184h) [Reset = X0000000h]

ADCINLTRIM5 is shown in Figure 24-201 and described in Table 24-179.

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ADC Linearity Trim 5 Register

Figure 24-201 ADCINLTRIM5 Register
313029282726252423222120191817161514131211109876543210
INLTRIM159TO128
R/W-Xh
Table 24-179 ADCINLTRIM5 Register Field Descriptions
BitFieldTypeResetDescription
31-0INLTRIM159TO128R/WXhADC Linearity Trim Bits 159-128.

This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications.

Reset type: XRSn

24.16.3.99 ADCINLTRIM6 Register (Offset = 188h) [Reset = X0000000h]

ADCINLTRIM6 is shown in Figure 24-202 and described in Table 24-180.

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ADC Linearity Trim 6 Register

Figure 24-202 ADCINLTRIM6 Register
313029282726252423222120191817161514131211109876543210
INLTRIM191TO160
R/W-Xh
Table 24-180 ADCINLTRIM6 Register Field Descriptions
BitFieldTypeResetDescription
31-0INLTRIM191TO160R/WXhADC Linearity Trim Bits 191-160.

This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications.

Reset type: XRSn

24.16.3.100 ADCREV2 Register (Offset = 18Eh) [Reset = 0205h]

ADCREV2 is shown in Figure 24-203 and described in Table 24-181.

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ADC Wrapper Revision Register

Figure 24-203 ADCREV2 Register
15141312111098
WRAPPERREV
R-2h
76543210
WRAPPERTYPE
R-5h
Table 24-181 ADCREV2 Register Field Descriptions
BitFieldTypeResetDescription
15-8WRAPPERREVR2hADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h. 01h : Wrapper for MicroADC with 32 SOC
02h : Wrapper for C2KADC with 32 SOC

Reset type: SYSRSn

7-0WRAPPERTYPER5hADC Wrapper Type. Always set to 5 for type 5 ADC Wrapper.

Reset type: SYSRSn

24.16.3.101 REP1CTL Register (Offset = 194h) [Reset = 00000000h]

REP1CTL is shown in Figure 24-204 and described in Table 24-182.

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ADC Trigger Repeater 1 Control Register

Figure 24-204 REP1CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
SWSYNCRESERVEDSYNCINSEL
R-0/W1S-0hR-0hR/W-0h
15141312111098
RESERVEDTRIGGER
R-0hR/W-0h
76543210
TRIGGEROVFPHASEOVFRESERVEDRESERVEDMODULEBUSYRESERVEDACTIVEMODEMODE
R/W1C-0hR/W1C-0hR-0hR-0hR-0hR-0hR-0hR/W-0h
Table 24-182 REP1CTL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23SWSYNCR-0/W1S0hTrigger repeater 1 software force sync. On a sync. event, all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved.

Note: SOCs associated with repeater 1 are not cleared.

Reset type: SYSRSn

22RESERVEDR0hReserved
21-16SYNCINSELR/W0hTrigger repeater 1 sync. input select. On a sync. event, all registers in repeater 1 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved.

Note: SOCs associated with repeater 1 are not cleared.
Refer to SOC spec for more details

Reset type: SYSRSn

15RESERVEDR0hReserved
14-8TRIGGERR/W0hADC Trigger Repeater 1 Trigger Select. Selects the trigger to modify via oversampling or undersampling.

00h REPTRIG0 - Software only
01h REPTRIG1 - CPU1 Timer 0, TINT0n
02h REPTRIG2 - CPU1 Timer 1, TINT1n
03h REPTRIG3 - CPU1 Timer 2, TINT2n
04h REPTRIG4 - GPIO, Input X-Bar INPUT5
05h REPTRIG5 - ePWM1, ADCSOCA
06h REPTRIG6 - ePWM1, ADCSOCB
07h REPTRIG7 - ePWM2, ADCSOCA
08h REPTRIG8 - ePWM2, ADCSOCB
09h REPTRIG9 - ePWM3, ADCSOCA
0Ah REPTRIG10 - ePWM3, ADCSOCB
0Bh REPTRIG11 - ePWM4, ADCSOCA
0Ch REPTRIG12 - ePWM4, ADCSOCB
0Dh REPTRIG13 - ePWM5, ADCSOCA
0Eh REPTRIG14 - ePWM5, ADCSOCB
0Fh REPTRIG15 - ePWM6, ADCSOCA
10h REPTRIG16 - ePWM6, ADCSOCB
11h REPTRIG17 - ePWM7, ADCSOCA
12h REPTRIG18 - ePWM7, ADCSOCB
13h REPTRIG19 - ePWM8, ADCSOCA
14h REPTRIG20 - ePWM8, ADCSOCB
15h REPTRIG21 - ePWM9, ADCSOCA
16h REPTRIG22 - ePWM9, ADCSOCB
17h REPTRIG23 - ePWM10, ADCSOCA
18h REPTRIG24 - ePWM10, ADCSOCB
19h REPTRIG25 - ePWM11, ADCSOCA
1Ah REPTRIG26 - ePWM11, ADCSOCB
1Bh REPTRIG27 - ePWM12, ADCSOCA
1Ch REPTRIG28 - ePWM12, ADCSOCB
1Dh REPTRIG29 - CPU2 Timer 0, TINT0n
1Eh REPTRIG30 - CPU2 Timer 1, TINT1n
1Fh REPTRIG31 - CPU2 Timer 2, TINT2n
20h - 4Fh - Reserved
50h REPTRIG80 eCAP1
51h REPTRIG81 eCAP2
52h REPTRIG82 eCAP3
53h REPTRIG83 eCAP4
54h REPTRIG84 eCAP5
55h REPTRIG85 eCAP6
56h REPTRIG86 eCAP7
57h REPTRIG87 eCAP8
58h REPTRIG88 - ePWM13, ADCSOCA
59h REPTRIG89 - ePWM13, ADCSOCB
5Ah REPTRIG90 - ePWM14, ADCSOCA
5Bh REPTRIG91 - ePWM14, ADCSOCB
5Ch REPTRIG92 - ePWM15, ADCSOCA
5Dh REPTRIG93 - ePWM15, ADCSOCB
5Eh REPTRIG94 - ePWM16, ADCSOCA
5Fh REPTRIG95 - ePWM16, ADCSOCB
60h REPTRIG96 - ePWM17, ADCSOCA
61h REPTRIG97 - ePWM17, ADCSOCB
62h REPTRIG98 - ePWM18, ADCSOCA
63h REPTRIG99 - ePWM18, ADCSOCB
64h - 7Fh - Reserved

Reset type: SYSRSn

7TRIGGEROVFR/W1C0hADC Trigger Repeater 1 Oversampled Trigger Overflow.

Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers (NCOUNT was not 0 or SOCs associated with Repeater 1 were still pending).

Writing a 1 will clear this flag.

Note: This flag won't be set in undersampling mode or when NSEL = 0
if a trigger arrives before the previous SOCs have completed, the trigger will be passed and the overflow flags of the SOCs that were still pending will be set.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

6PHASEOVFR/W1C0hADC Trigger Repeater 1 Phase Delay Overflow.

Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger (PHASECOUNT was not 0).

Writing a 1 will clear this flag.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

5RESERVEDR0hReserved
4RESERVEDR0hReserved
3MODULEBUSYR0hADC Trigger Repeater 1 Module Busy indicator. In oversampling mode:

0 = Repeater 1 is idle and can accept a new repeated trigger in oversampling mode
1 = Repeater 1 still has repeated triggers remaining (NCOUNT > 0) or associated SOCs are still pending (SOCBUSY is 1)

If a new oversampled trigger is received while the module is still busy, the TRIGGEROVF bit will be set and the trigger will be ignored.

Reset type: SYSRSn

2RESERVEDR0hReserved
1ACTIVEMODER0hWhen a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't cause any changes in functionality until the module becomes idle and then a new trigger is received.

0 = module is oversampling
1 = module is undersampling

Reset type: SYSRSn

0MODER/W0hADC trigger repeater 1 mode selection. Select either oversampling or undersampling mode.

In oversampling mode, when the trigger selected by REP1CTL.TRIGSEL is received, the repeater will repeat the trigger REP1N.NSEL + 1 times.

In undersampling mode, when the trigger selected by REP1CTL.TRIGSEL is received the first time, the repeater will pass the trigger through. The next REP1N.NSEL triggers will be ignored.

0 = oversampling
1 = undersampling

Reset type: SYSRSn

24.16.3.102 REP1N Register (Offset = 198h) [Reset = 00000000h]

REP1N is shown in Figure 24-205 and described in Table 24-183.

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ADC Trigger Repeater 1 N Select Register

Figure 24-205 REP1N Register
313029282726252423222120191817161514131211109876543210
RESERVEDNCOUNTRESERVEDNSEL
R-0hR-0hR-0hR/W-0h
Table 24-183 REP1N Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-16NCOUNTR0hADC trigger repeater 1 trigger count.

In oversampling mode, indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP1CTL.TRIGSEL while NCOUNT is not 0 (the repeater is still busy generating the repeated triggers) then the trigger will be ignored and REP1CTL.TRIGOVF will be set to 1.

In undersampling mode, indicates the number of triggers remaining to be supressed.

Reset type: SYSRSn

15-7RESERVEDR0hReserved
6-0NSELR/W0hADC Trigger Repeater 1 selection of number of triggers.

In oversampling mode, selects the number of repeated triggers. For each trigger received corresponding to REP1CTL.TRIGSEL, NSEL + 1 triggers will be generated.

0 = 1 trigger is generated (pass-through)
1 = 2 triggers are generated
2 = 3 triggers are generated
...
127 = 128 triggers are generated

In undersampling mode, selects the number triggers to be supressed. 1 out NSEL + 1 triggers received corresponding to REP1CTL.TRIGSEL will be passed through (the first trigger will be passed through and the subsequent NSEL triggers will be supressed).

0 = all triggers are passed
1 = 1 out of 2 triggers are passed
2 = 1 out of 3 triggers are passed
...
127 = 1 out of 128 triggers are passed

Reset type: SYSRSn

24.16.3.103 REP1PHASE Register (Offset = 19Ch) [Reset = 00000000h]

REP1PHASE is shown in Figure 24-206 and described in Table 24-184.

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ADC Trigger Repeater 1 Phase Select Register

Figure 24-206 REP1PHASE Register
313029282726252423222120191817161514131211109876543210
PHASECOUNTPHASE
R-0hR/W-0h
Table 24-184 REP1PHASE Register Field Descriptions
BitFieldTypeResetDescription
31-16PHASECOUNTR0hADC trigger repeater 1 phase delay status. When the trigger selected by REP1CTL.TRIGSEL is received, this register will start counting down from PHASECOUNT until the counter reaches 0, at which point the trigger will be passed on to the repeater re-trigger logic.

If the trigger selected by REP1CTL.TRIGSEL is recieved when PHASECOUNT is not 0 (the phase delay logic is busy from the previous trigger) then the new trigger will be ignored and REP1CTL.PHASEOVF will be set to 1.

Reset type: SYSRSn

15-0PHASER/W0hADC trigger repeater 1 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic.

0 = trigger is passed through without delay
1 = trigger is delayed by 1 SYSCLK
2 = trigger is delayed by 2 SYSCLKs
...
65535 = trigger is delayed by 65535 SYSCLKs

Reset type: SYSRSn

24.16.3.104 REP1SPREAD Register (Offset = 1A0h) [Reset = 00000000h]

REP1SPREAD is shown in Figure 24-207 and described in Table 24-185.

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ADC Trigger Repeater 1 Spread Select Register

Figure 24-207 REP1SPREAD Register
313029282726252423222120191817161514131211109876543210
SPREADCOUNTSPREAD
R-0hR/W-0h
Table 24-185 REP1SPREAD Register Field Descriptions
BitFieldTypeResetDescription
31-16SPREADCOUNTR0hADC trigger repeater 1 spread status. When a trigger is sent to the ADC in oversampling mode, this register will start counting down from SPREAD until SPREADCOUNT equals 0.

The next repeated trigger to the ADC in oversampling mode will not occur until SPREADCOUNT is 0 (minimum time is complete) and REP1CTL.BUSY = 0 (SOCs associated with trigger repeater 1 are no longer pending).

Reset type: SYSRSn

15-0SPREADR/W0hADC trigger repeater 1 spread delay configuration. In oversampling mode, defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC.

If SPREAD is less than the time needed for all SOCs associated with repeater 1 to sample and convert, then the repeater will generate triggers as fast as the ADC can convert the associated conversions.

If SPREAD is greater than the time needed for all SOCs associated with repeater 1 to sample and convert, then repeated triggers to the ADC will be SPREAD SYSCLK cycles apart.

0 = oversampled repeated triggers occur as fast as the ADC can sample and convert associated SOCs
1 = time between repeated triggers is at least 1 SYSCLKs
2 = time between repeated triggers is at least 2 SYSCLKs
...
65535 = time between repeated triggers is at least 65535 SYSCLKs

Reset type: SYSRSn

24.16.3.105 REP1FRC Register (Offset = 1A4h) [Reset = 0000h]

REP1FRC is shown in Figure 24-208 and described in Table 24-186.

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ADC Trigger Repeater 1 Software Force Register

Figure 24-208 REP1FRC Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDSWFRC
R-0hR-0/W1S-0h
Table 24-186 REP1FRC Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0hReserved
0SWFRCR-0/W1S0hWrite 1 to force a trigger to repeat block 1 input regardless of the value of TRIGGER.

Always reads 0.

Reset type: SYSRSn

24.16.3.106 REP2CTL Register (Offset = 1B4h) [Reset = 00000000h]

REP2CTL is shown in Figure 24-209 and described in Table 24-187.

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ADC Trigger Repeater 2 Control Register

Figure 24-209 REP2CTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
SWSYNCRESERVEDSYNCINSEL
R-0/W1S-0hR-0hR/W-0h
15141312111098
RESERVEDTRIGGER
R-0hR/W-0h
76543210
TRIGGEROVFPHASEOVFRESERVEDRESERVEDMODULEBUSYRESERVEDACTIVEMODEMODE
R/W1C-0hR/W1C-0hR-0hR-0hR-0hR-0hR-0hR/W-0h
Table 24-187 REP2CTL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23SWSYNCR-0/W1S0hTrigger repeater 2 software force sync. On a sync. event, all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved.

Note: SOCs associated with repeater 2 are not cleared.

Reset type: SYSRSn

22RESERVEDR0hReserved
21-16SYNCINSELR/W0hTrigger repeater 2 sync. input select. On a sync. event, all registers in repeater 2 are reset to a ready and waiting state. Values of NSEL, PHASE, and MODE are preserved.

Note: SOCs associated with repeater 2 are not cleared.
Refer to SOC spec for more details

Reset type: SYSRSn

15RESERVEDR0hReserved
14-8TRIGGERR/W0hADC Trigger Repeater 2 Trigger Select. Selects the trigger to modify via oversampling or undersampling.

00h REPTRIG0 - Software only
01h REPTRIG1 - CPU1 Timer 0, TINT0n
02h REPTRIG2 - CPU1 Timer 1, TINT1n
03h REPTRIG3 - CPU1 Timer 2, TINT2n
04h REPTRIG4 - GPIO, Input X-Bar INPUT5
05h REPTRIG5 - ePWM1, ADCSOCA
06h REPTRIG6 - ePWM1, ADCSOCB
07h REPTRIG7 - ePWM2, ADCSOCA
08h REPTRIG8 - ePWM2, ADCSOCB
09h REPTRIG9 - ePWM3, ADCSOCA
0Ah REPTRIG10 - ePWM3, ADCSOCB
0Bh REPTRIG11 - ePWM4, ADCSOCA
0Ch REPTRIG12 - ePWM4, ADCSOCB
0Dh REPTRIG13 - ePWM5, ADCSOCA
0Eh REPTRIG14 - ePWM5, ADCSOCB
0Fh REPTRIG15 - ePWM6, ADCSOCA
10h REPTRIG16 - ePWM6, ADCSOCB
11h REPTRIG17 - ePWM7, ADCSOCA
12h REPTRIG18 - ePWM7, ADCSOCB
13h REPTRIG19 - ePWM8, ADCSOCA
14h REPTRIG20 - ePWM8, ADCSOCB
15h REPTRIG21 - ePWM9, ADCSOCA
16h REPTRIG22 - ePWM9, ADCSOCB
17h REPTRIG23 - ePWM10, ADCSOCA
18h REPTRIG24 - ePWM10, ADCSOCB
19h REPTRIG25 - ePWM11, ADCSOCA
1Ah REPTRIG26 - ePWM11, ADCSOCB
1Bh REPTRIG27 - ePWM12, ADCSOCA
1Ch REPTRIG28 - ePWM12, ADCSOCB
1Dh REPTRIG29 - CPU2 Timer 0, TINT0n
1Eh REPTRIG30 - CPU2 Timer 1, TINT1n
1Fh REPTRIG31 - CPU2 Timer 2, TINT2n
20h - 4Fh - Reserved
50h REPTRIG80 eCAP1
51h REPTRIG81 eCAP2
52h REPTRIG82 eCAP3
53h REPTRIG83 eCAP4
54h REPTRIG84 eCAP5
55h REPTRIG85 eCAP6
56h REPTRIG86 eCAP7
57h REPTRIG87 eCAP8
58h REPTRIG88 - ePWM13, ADCSOCA
59h REPTRIG89 - ePWM13, ADCSOCB
5Ah REPTRIG90 - ePWM14, ADCSOCA
5Bh REPTRIG91 - ePWM14, ADCSOCB
5Ch REPTRIG92 - ePWM15, ADCSOCA
5Dh REPTRIG93 - ePWM15, ADCSOCB
5Eh REPTRIG94 - ePWM16, ADCSOCA
5Fh REPTRIG95 - ePWM16, ADCSOCB
60h REPTRIG96 - ePWM17, ADCSOCA
61h REPTRIG97 - ePWM17, ADCSOCB
62h REPTRIG98 - ePWM18, ADCSOCA
63h REPTRIG99 - ePWM18, ADCSOCB
64h - 7Fh - Reserved

Reset type: SYSRSn

7TRIGGEROVFR/W1C0hADC Trigger Repeater 2 Oversampled Trigger Overflow.

Indicates that a trigger was dropped because a trigger arrived while the repeater was still generating repeated oversampled triggers (NCOUNT was not 0 or SOCs associated with Repeater 2 were still pending).

Writing a 1 will clear this flag.

Note: This flag won't be set in undersampling mode or when NSEL = 0
if a trigger arrives before the previous SOCs have completed, the trigger will be passed and the overflow flags of the SOCs that were still pending will be set.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

6PHASEOVFR/W1C0hADC Trigger Repeater 2 Phase Delay Overflow.

Indicates that a trigger was dropped because a trigger arrived when the phase delay logic was still waiting to send the delayed trigger (PHASECOUNT was not 0).

Writing a 1 will clear this flag.

Note: If software sets the clear bit on the same cycle that hardware is trying to set the flag bit, then hardware has priority and the overflow bit will not be set

Reset type: SYSRSn

5RESERVEDR0hReserved
4RESERVEDR0hReserved
3MODULEBUSYR0hADC Trigger Repeater 2 Module Busy indicator. In oversampling mode:

0 = Repeater 2 is idle and can accept a new repeated trigger in oversampling mode
1 = Repeater 2 still has repeated triggers remaining (NCOUNT > 0) or associated SOCs are still pending (SOCBUSY is 1)

If a new oversampled trigger is received while the module is still busy, the TRIGGEROVF bit will be set and the trigger will be ignored.

Reset type: SYSRSn

2RESERVEDR0hReserved
1ACTIVEMODER0hWhen a trigger is recived in oversampling or undersampling mode the value of MODE is copied to ACTIVEMODE. ACTIVEMODE determines if the repeater will repeat of filter triggers. Changes to MODE while the repeater is working therefore won't cause any changes in functionality until the module becomes idle and then a new trigger is received.

0 = module is oversampling
1 = module is undersampling

Reset type: SYSRSn

0MODER/W0hADC trigger repeater 2 mode selection. Select either oversampling or undersampling mode.

In oversampling mode, when the trigger selected by REP2CTL.TRIGSEL is received, the repeater will repeat the trigger REP2N.NSEL + 1 times.

In undersampling mode, when the trigger selected by REP2CTL.TRIGSEL is received the first time, the repeater will pass the trigger through. The next REP2N.NSEL triggers will be ignored.

0 = oversampling
1 = undersampling

Reset type: SYSRSn

24.16.3.107 REP2N Register (Offset = 1B8h) [Reset = 00000000h]

REP2N is shown in Figure 24-210 and described in Table 24-188.

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ADC Trigger Repeater 2 N Select Register

Figure 24-210 REP2N Register
313029282726252423222120191817161514131211109876543210
RESERVEDNCOUNTRESERVEDNSEL
R-0hR-0hR-0hR/W-0h
Table 24-188 REP2N Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-16NCOUNTR0hADC trigger repeater 2 trigger count.

In oversampling mode, indicates the number of triggers remaining to be generated. If a trigger is received corresponding to REP2CTL.TRIGSEL while NCOUNT is not 0 (the repeater is still busy generating the repeated triggers) then the trigger will be ignored and REP2CTL.TRIGOVF will be set to 1.

In undersampling mode, indicates the number of triggers remaining to be supressed.

Reset type: SYSRSn

15-7RESERVEDR0hReserved
6-0NSELR/W0hADC Trigger Repeater 2 selection of number of triggers.

In oversampling mode, selects the number of repeated triggers. For each trigger received corresponding to REP2CTL.TRIGSEL, NSEL + 1 triggers will be generated.

0 = 1 trigger is generated (pass-through)
1 = 2 triggers are generated
2 = 3 triggers are generated
...
127 = 128 triggers are generated

In undersampling mode, selects the number triggers to be supressed. 1 out NSEL + 1 triggers received corresponding to REP2CTL.TRIGSEL will be passed through (the first trigger will be passed through and the subsequent NSEL triggers will be supressed).

0 = all triggers are passed
1 = 1 out of 2 triggers are passed
2 = 1 out of 3 triggers are passed
...
127 = 1 out of 128 triggers are passed

Reset type: SYSRSn

24.16.3.108 REP2PHASE Register (Offset = 1BCh) [Reset = 00000000h]

REP2PHASE is shown in Figure 24-211 and described in Table 24-189.

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ADC Trigger Repeater 2 Phase Select Register

Figure 24-211 REP2PHASE Register
313029282726252423222120191817161514131211109876543210
PHASECOUNTPHASE
R-0hR/W-0h
Table 24-189 REP2PHASE Register Field Descriptions
BitFieldTypeResetDescription
31-16PHASECOUNTR0hADC trigger repeater 2 phase delay status. When the trigger selected by REP2CTL.TRIGSEL is received, this register will start counting down from PHASECOUNT until the counter reaches 0, at which point the trigger will be passed on to the repeater re-trigger logic.

If the trigger selected by REP2CTL.TRIGSEL is recieved when PHASECOUNT is not 0 (the phase delay logic is busy from the previous trigger) then the new trigger will be ignored and REP2CTL.PHASEOVF will be set to 1.

Reset type: SYSRSn

15-0PHASER/W0hADC trigger repeater 2 phase delay configuration. Defines the number of SYSCLKs to delay the selected trigger before passing it on to the re-triggering logic.

0 = trigger is passed through without delay
1 = trigger is delayed by 1 SYSCLK
2 = trigger is delayed by 2 SYSCLKs
...
65535 = trigger is delayed by 65535 SYSCLKs

Reset type: SYSRSn

24.16.3.109 REP2SPREAD Register (Offset = 1C0h) [Reset = 00000000h]

REP2SPREAD is shown in Figure 24-212 and described in Table 24-190.

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ADC Trigger Repeater 2 Spread Select Register

Figure 24-212 REP2SPREAD Register
313029282726252423222120191817161514131211109876543210
SPREADCOUNTSPREAD
R-0hR/W-0h
Table 24-190 REP2SPREAD Register Field Descriptions
BitFieldTypeResetDescription
31-16SPREADCOUNTR0hADC trigger repeater 2 spread status. When a trigger is sent to the ADC in oversampling mode, this register will start counting down from SPREAD until SPREADCOUNT equals 0.

The next repeated trigger to the ADC in oversampling mode will not occur until SPREADCOUNT is 0 (minimum time is complete) and REP2CTL.BUSY = 0 (SOCs associated with trigger repeater 2 are no longer pending).

Reset type: SYSRSn

15-0SPREADR/W0hADC trigger repeater 2 spread delay configuration. In oversampling mode, defines the minimum number of SYSCLKs to wait before creating the next repeated trigger to the ADC.

If SPREAD is less than the time needed for all SOCs associated with repeater 2 to sample and convert, then the repeater will generate triggers as fast as the ADC can convert the associated conversions.

If SPREAD is greater than the time needed for all SOCs associated with repeater 2 to sample and convert, then repeated triggers to the ADC will be SPREAD SYSCLK cycles apart.

0 = oversampled repeated triggers occur as fast as the ADC can sample and convert associated SOCs
1 = time between repeated triggers is at least 1 SYSCLKs
2 = time between repeated triggers is at least 2 SYSCLKs
...
65535 = time between repeated triggers is at least 65535 SYSCLKs

Reset type: SYSRSn

24.16.3.110 REP2FRC Register (Offset = 1C4h) [Reset = 0000h]

REP2FRC is shown in Figure 24-213 and described in Table 24-191.

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ADC Trigger Repeater 2 Software Force Register

Figure 24-213 REP2FRC Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDSWFRC
R-0hR-0/W1S-0h
Table 24-191 REP2FRC Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0hReserved
0SWFRCR-0/W1S0hWrite 1 to force a trigger to repeat block 2 input regardless of the value of TRIGGER.

Always reads 0.

Reset type: SYSRSn

24.16.3.111 ADCPPB1LIMIT Register (Offset = 1D4h) [Reset = 0000h]

ADCPPB1LIMIT is shown in Figure 24-214 and described in Table 24-192.

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ADC PPB1Conversion Count Limit Register

Figure 24-214 ADCPPB1LIMIT Register
15141312111098
RESERVEDLIMIT
R-0hR/W-0h
76543210
LIMIT
R/W-0h
Table 24-192 ADCPPB1LIMIT Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0LIMITR/W0hPost Processing Block 1 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM.

To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode.

Reset type: SYSRSn

24.16.3.112 ADCPPBP1PCOUNT Register (Offset = 1D8h) [Reset = 0000h]

ADCPPBP1PCOUNT is shown in Figure 24-215 and described in Table 24-193.

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ADC PPB1 Partial Conversion Count Register

Figure 24-215 ADCPPBP1PCOUNT Register
15141312111098
RESERVEDPCOUNT
R-0hR-0h
76543210
PCOUNT
R-0h
Table 24-193 ADCPPBP1PCOUNT Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PCOUNTR0hPost Processing Block 1 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB1PSUM this register is incremented by 1.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information).

Reset type: SYSRSn

24.16.3.113 ADCPPB1CONFIG2 Register (Offset = 1DCh) [Reset = 0000h]

ADCPPB1CONFIG2 is shown in Figure 24-216 and described in Table 24-194.

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ADC PPB1 Sum Shift Register

Figure 24-216 ADCPPB1CONFIG2 Register
15141312111098
COMPSELRESERVEDOSINTSELSWSYNCRESERVEDSYNCINSEL
R/W-0hR-0hR/W-0hR-0/W1S-0hR-0hR/W-0h
76543210
SYNCINSELSHIFT
R/W-0hR/W-0h
Table 24-194 ADCPPB1CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
15-14COMPSELR/W0hPost Processing Block 1 Compare Source Select. This field determines whether ADCPPB1RESULT, ADCPPB1PSUM, or ADCPPB1SUM is used for the zero-crossing detect logic and threshold compare.

00 = ADCPPB1RESULT is used for compare logic
01 = ADCPPB1PSUM is used for compare logic
10 = ADCPPB1SUM is used for compare logic
11 = Reserved

Note: when ADCPPB1PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB1LIMIT equals ADCPPB1COUNT) the ADCPPB1PSUM register will be cleared and the final sum will be loaded into ADCPPB1SUM. For this sample, the final sum, ADCPPB1SUM will be used for the compariosn instead of ADCPPB1PSUM.

Reset type: SYSRSn

13RESERVEDR0hReserved
12OSINTSELR/W0hPost Processing Block 1 Interrupt Source Select.

OSINT1 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT1 in addition to a PCOUNT = LIMIT event.

0 = OSINT1 will be generated from PCOUNT = LIMIT only
1 = OSTIN1 will be generated form PCOUNT = LIMIT or a sync. event.

Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored.

Reset type: SYSRSn

11SWSYNCR-0/W1S0hPPB 1 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset.

Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur.

Reset type: SYSRSn

10RESERVEDR0hReserved
9-4SYNCINSELR/W0hPPB 1 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset.
Refer to SOC spec for details

Reset type: SYSRSn

3-0SHIFTR/W0hPost Processing Block 1 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM.

0 : no right shift
1 : SUM = PSUM >> 1
2 : SUM = PSUM >> 2
...
10 : SUM = PSUM >> 10
11 - 15 : Reserved

Reset type: SYSRSn

24.16.3.114 ADCPPB1PSUM Register (Offset = 1E0h) [Reset = 00000000h]

ADCPPB1PSUM is shown in Figure 24-217 and described in Table 24-195.

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ADC PPB1 Partial Sum Register

Figure 24-217 ADCPPB1PSUM Register
313029282726252423222120191817161514131211109876543210
SIGNPSUM
R-0hR-0h
Table 24-195 ADCPPB1PSUM Register Field Descriptions
BitFieldTypeResetDescription
31-24SIGNR0hSign Extended Bits. These bits reflect the same value as bit 23.

Reset type: SYSRSn

23-0PSUMR0hPost Processing Block 1 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result is subsequently accumulated into this register.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information).

Reset type: SYSRSn

24.16.3.115 ADCPPB1PMAX Register (Offset = 1E4h) [Reset = 00000000h]

ADCPPB1PMAX is shown in Figure 24-218 and described in Table 24-196.

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ADC PPB1 Partial Max Register

Figure 24-218 ADCPPB1PMAX Register
313029282726252423222120191817161514131211109876543210
SIGNPMAX
R-0hR-0h
Table 24-196 ADCPPB1PMAX Register Field Descriptions
BitFieldTypeResetDescription
31-17SIGNR0hSign Extended Bits. These bits reflect the same value as bit 16.

Reset type: SYSRSn

16-0PMAXR0hPost Processing Block 1 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is larger.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information).

Reset type: SYSRSn

24.16.3.116 ADCPPB1PMAXI Register (Offset = 1E8h) [Reset = 0000h]

ADCPPB1PMAXI is shown in Figure 24-219 and described in Table 24-197.

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ADC PPB1 Partial Max Index Register

Figure 24-219 ADCPPB1PMAXI Register
15141312111098
RESERVEDPMAXI
R-0hR-0h
76543210
PMAXI
R-0h
Table 24-197 ADCPPB1PMAXI Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PMAXIR0hPost Processing Block 1 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information).

Reset type: SYSRSn

24.16.3.117 ADCPPB1PMIN Register (Offset = 1ECh) [Reset = 00000000h]

ADCPPB1PMIN is shown in Figure 24-220 and described in Table 24-198.

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ADC PPB1 Partial MIN Register

Figure 24-220 ADCPPB1PMIN Register
313029282726252423222120191817161514131211109876543210
SIGNPMIN
R-0hR-0h
Table 24-198 ADCPPB1PMIN Register Field Descriptions
BitFieldTypeResetDescription
31-17SIGNR0hSign Extended Bits. These bits reflect the same value as bit 16.

Reset type: SYSRSn

16-0PMINR0hPost Processing Block 1 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT the result replaces this register if it is smaller.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information).

Reset type: SYSRSn

24.16.3.118 ADCPPB1PMINI Register (Offset = 1F0h) [Reset = 0000h]

ADCPPB1PMINI is shown in Figure 24-221 and described in Table 24-199.

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ADC PPB1 Partial Min Index Register

Figure 24-221 ADCPPB1PMINI Register
15141312111098
RESERVEDPMINI
R-0hR-0h
76543210
PMINI
R-0h
Table 24-199 ADCPPB1PMINI Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PMINIR0hPost Processing Block 1 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB1RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB1 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB1RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB1RESULT timing information).

Reset type: SYSRSn

24.16.3.119 ADCPPB1TRIPLO2 Register (Offset = 1F4h) [Reset = 00000000h]

ADCPPB1TRIPLO2 is shown in Figure 24-222 and described in Table 24-200.

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ADC PPB1 Extended Trip Low Register

Figure 24-222 ADCPPB1TRIPLO2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITLO
R-0hR/W-0h
Table 24-200 ADCPPB1TRIPLO2 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0LIMITLOR/W0hADC Post Processing Block 1 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB1TRIPLO.LIMITLO2EN = 1.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPLO2[23:17] will be ignored in 16 bit mode
- TRIPLO2[23:13] will be ignored in 12 bit mode

Reset type: SYSRSn

24.16.3.120 ADCPPB2LIMIT Register (Offset = 208h) [Reset = 0000h]

ADCPPB2LIMIT is shown in Figure 24-223 and described in Table 24-201.

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ADC PPB2Conversion Count Limit Register

Figure 24-223 ADCPPB2LIMIT Register
15141312111098
RESERVEDLIMIT
R-0hR/W-0h
76543210
LIMIT
R/W-0h
Table 24-201 ADCPPB2LIMIT Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0LIMITR/W0hPost Processing Block 2 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM.

To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode.

Reset type: SYSRSn

24.16.3.121 ADCPPBP2PCOUNT Register (Offset = 20Ch) [Reset = 0000h]

ADCPPBP2PCOUNT is shown in Figure 24-224 and described in Table 24-202.

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ADC PPB2 Partial Conversion Count Register

Figure 24-224 ADCPPBP2PCOUNT Register
15141312111098
RESERVEDPCOUNT
R-0hR-0h
76543210
PCOUNT
R-0h
Table 24-202 ADCPPBP2PCOUNT Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PCOUNTR0hPost Processing Block 2 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB2PSUM this register is incremented by 1.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information).

Reset type: SYSRSn

24.16.3.122 ADCPPB2CONFIG2 Register (Offset = 210h) [Reset = 0000h]

ADCPPB2CONFIG2 is shown in Figure 24-225 and described in Table 24-203.

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ADC PPB2 Sum Shift Register

Figure 24-225 ADCPPB2CONFIG2 Register
15141312111098
COMPSELRESERVEDOSINTSELSWSYNCRESERVEDSYNCINSEL
R/W-0hR-0hR/W-0hR-0/W1S-0hR-0hR/W-0h
76543210
SYNCINSELSHIFT
R/W-0hR/W-0h
Table 24-203 ADCPPB2CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
15-14COMPSELR/W0hPost Processing Block 2 Compare Source Select. This field determines whether ADCPPB2RESULT, ADCPPB2PSUM, or ADCPPB2SUM is used for the zero-crossing detect logic and threshold compare.

00 = ADCPPB2RESULT is used for compare logic
01 = ADCPPB2PSUM is used for compare logic
10 = ADCPPB2SUM is used for compare logic
11 = Reserved

Note: when ADCPPB2PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB2LIMIT equals ADCPPB2COUNT) the ADCPPB2PSUM register will be cleared and the final sum will be loaded into ADCPPB2SUM. For this sample, the final sum, ADCPPB2SUM will be used for the compariosn instead of ADCPPB2PSUM.

Reset type: SYSRSn

13RESERVEDR0hReserved
12OSINTSELR/W0hPost Processing Block 2 Interrupt Source Select.

OSINT2 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT2 in addition to a PCOUNT = LIMIT event.

0 = OSINT2 will be generated from PCOUNT = LIMIT only
1 = OSTIN2 will be generated form PCOUNT = LIMIT or a sync. event.

Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored.

Reset type: SYSRSn

11SWSYNCR-0/W1S0hPPB 2 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset.

Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur.

Reset type: SYSRSn

10RESERVEDR0hReserved
9-4SYNCINSELR/W0hPPB 2 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset.
Refer to SOC spec for details

Reset type: SYSRSn

3-0SHIFTR/W0hPost Processing Block 2 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM.

0 : no right shift
1 : SUM = PSUM >> 1
2 : SUM = PSUM >> 2
...
10 : SUM = PSUM >> 10
11 - 15 : Reserved

Reset type: SYSRSn

24.16.3.123 ADCPPB2PSUM Register (Offset = 214h) [Reset = 00000000h]

ADCPPB2PSUM is shown in Figure 24-226 and described in Table 24-204.

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ADC PPB2 Partial Sum Register

Figure 24-226 ADCPPB2PSUM Register
313029282726252423222120191817161514131211109876543210
SIGNPSUM
R-0hR-0h
Table 24-204 ADCPPB2PSUM Register Field Descriptions
BitFieldTypeResetDescription
31-24SIGNR0hSign Extended Bits. These bits reflect the same value as bit 23.

Reset type: SYSRSn

23-0PSUMR0hPost Processing Block 2 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result is subsequently accumulated into this register.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information).

Reset type: SYSRSn

24.16.3.124 ADCPPB2PMAX Register (Offset = 218h) [Reset = 00000000h]

ADCPPB2PMAX is shown in Figure 24-227 and described in Table 24-205.

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ADC PPB2 Partial Max Register

Figure 24-227 ADCPPB2PMAX Register
313029282726252423222120191817161514131211109876543210
SIGNPMAX
R-0hR-0h
Table 24-205 ADCPPB2PMAX Register Field Descriptions
BitFieldTypeResetDescription
31-17SIGNR0hSign Extended Bits. These bits reflect the same value as bit 16.

Reset type: SYSRSn

16-0PMAXR0hPost Processing Block 2 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is larger.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information).

Reset type: SYSRSn

24.16.3.125 ADCPPB2PMAXI Register (Offset = 21Ch) [Reset = 0000h]

ADCPPB2PMAXI is shown in Figure 24-228 and described in Table 24-206.

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ADC PPB2 Partial Max Index Register

Figure 24-228 ADCPPB2PMAXI Register
15141312111098
RESERVEDPMAXI
R-0hR-0h
76543210
PMAXI
R-0h
Table 24-206 ADCPPB2PMAXI Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PMAXIR0hPost Processing Block 2 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information).

Reset type: SYSRSn

24.16.3.126 ADCPPB2PMIN Register (Offset = 220h) [Reset = 00000000h]

ADCPPB2PMIN is shown in Figure 24-229 and described in Table 24-207.

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ADC PPB2 Partial MIN Register

Figure 24-229 ADCPPB2PMIN Register
313029282726252423222120191817161514131211109876543210
SIGNPMIN
R-0hR-0h
Table 24-207 ADCPPB2PMIN Register Field Descriptions
BitFieldTypeResetDescription
31-17SIGNR0hSign Extended Bits. These bits reflect the same value as bit 16.

Reset type: SYSRSn

16-0PMINR0hPost Processing Block 2 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT the result replaces this register if it is smaller.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information).

Reset type: SYSRSn

24.16.3.127 ADCPPB2PMINI Register (Offset = 224h) [Reset = 0000h]

ADCPPB2PMINI is shown in Figure 24-230 and described in Table 24-208.

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ADC PPB2 Partial Min Index Register

Figure 24-230 ADCPPB2PMINI Register
15141312111098
RESERVEDPMINI
R-0hR-0h
76543210
PMINI
R-0h
Table 24-208 ADCPPB2PMINI Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PMINIR0hPost Processing Block 2 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB2RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB2 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB2RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB2RESULT timing information).

Reset type: SYSRSn

24.16.3.128 ADCPPB2TRIPLO2 Register (Offset = 228h) [Reset = 00000000h]

ADCPPB2TRIPLO2 is shown in Figure 24-231 and described in Table 24-209.

Return to the Summary Table.

ADC PPB2 Extended Trip Low Register

Figure 24-231 ADCPPB2TRIPLO2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITLO
R-0hR/W-0h
Table 24-209 ADCPPB2TRIPLO2 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0LIMITLOR/W0hADC Post Processing Block 2 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB2TRIPLO.LIMITLO2EN = 1.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPLO2[23:17] will be ignored in 16 bit mode
- TRIPLO2[23:13] will be ignored in 12 bit mode

Reset type: SYSRSn

24.16.3.129 ADCPPB3LIMIT Register (Offset = 23Ch) [Reset = 0000h]

ADCPPB3LIMIT is shown in Figure 24-232 and described in Table 24-210.

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ADC PPB3Conversion Count Limit Register

Figure 24-232 ADCPPB3LIMIT Register
15141312111098
RESERVEDLIMIT
R-0hR/W-0h
76543210
LIMIT
R/W-0h
Table 24-210 ADCPPB3LIMIT Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0LIMITR/W0hPost Processing Block 3 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM.

To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode.

Reset type: SYSRSn

24.16.3.130 ADCPPBP3PCOUNT Register (Offset = 240h) [Reset = 0000h]

ADCPPBP3PCOUNT is shown in Figure 24-233 and described in Table 24-211.

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ADC PPB3 Partial Conversion Count Register

Figure 24-233 ADCPPBP3PCOUNT Register
15141312111098
RESERVEDPCOUNT
R-0hR-0h
76543210
PCOUNT
R-0h
Table 24-211 ADCPPBP3PCOUNT Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PCOUNTR0hPost Processing Block 3 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB3PSUM this register is incremented by 1.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information).

Reset type: SYSRSn

24.16.3.131 ADCPPB3CONFIG2 Register (Offset = 244h) [Reset = 0000h]

ADCPPB3CONFIG2 is shown in Figure 24-234 and described in Table 24-212.

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ADC PPB3 Sum Shift Register

Figure 24-234 ADCPPB3CONFIG2 Register
15141312111098
COMPSELRESERVEDOSINTSELSWSYNCRESERVEDSYNCINSEL
R/W-0hR-0hR/W-0hR-0/W1S-0hR-0hR/W-0h
76543210
SYNCINSELSHIFT
R/W-0hR/W-0h
Table 24-212 ADCPPB3CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
15-14COMPSELR/W0hPost Processing Block 3 Compare Source Select. This field determines whether ADCPPB3RESULT, ADCPPB3PSUM, or ADCPPB3SUM is used for the zero-crossing detect logic and threshold compare.

00 = ADCPPB3RESULT is used for compare logic
01 = ADCPPB3PSUM is used for compare logic
10 = ADCPPB3SUM is used for compare logic
11 = Reserved

Note: when ADCPPB3PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB3LIMIT equals ADCPPB3COUNT) the ADCPPB3PSUM register will be cleared and the final sum will be loaded into ADCPPB3SUM. For this sample, the final sum, ADCPPB3SUM will be used for the compariosn instead of ADCPPB3PSUM.

Reset type: SYSRSn

13RESERVEDR0hReserved
12OSINTSELR/W0hPost Processing Block 3 Interrupt Source Select.

OSINT3 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT3 in addition to a PCOUNT = LIMIT event.

0 = OSINT3 will be generated from PCOUNT = LIMIT only
1 = OSTIN3 will be generated form PCOUNT = LIMIT or a sync. event.

Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored.

Reset type: SYSRSn

11SWSYNCR-0/W1S0hPPB 3 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset.

Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur.

Reset type: SYSRSn

10RESERVEDR0hReserved
9-4SYNCINSELR/W0hPPB 3 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset.
Refer to SOC spec for details

Reset type: SYSRSn

3-0SHIFTR/W0hPost Processing Block 3 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM.

0 : no right shift
1 : SUM = PSUM >> 1
2 : SUM = PSUM >> 2
...
10 : SUM = PSUM >> 10
11 - 15 : Reserved

Reset type: SYSRSn

24.16.3.132 ADCPPB3PSUM Register (Offset = 248h) [Reset = 00000000h]

ADCPPB3PSUM is shown in Figure 24-235 and described in Table 24-213.

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ADC PPB3 Partial Sum Register

Figure 24-235 ADCPPB3PSUM Register
313029282726252423222120191817161514131211109876543210
SIGNPSUM
R-0hR-0h
Table 24-213 ADCPPB3PSUM Register Field Descriptions
BitFieldTypeResetDescription
31-24SIGNR0hSign Extended Bits. These bits reflect the same value as bit 23.

Reset type: SYSRSn

23-0PSUMR0hPost Processing Block 3 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result is subsequently accumulated into this register.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information).

Reset type: SYSRSn

24.16.3.133 ADCPPB3PMAX Register (Offset = 24Ch) [Reset = 00000000h]

ADCPPB3PMAX is shown in Figure 24-236 and described in Table 24-214.

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ADC PPB3 Partial Max Register

Figure 24-236 ADCPPB3PMAX Register
313029282726252423222120191817161514131211109876543210
SIGNPMAX
R-0hR-0h
Table 24-214 ADCPPB3PMAX Register Field Descriptions
BitFieldTypeResetDescription
31-17SIGNR0hSign Extended Bits. These bits reflect the same value as bit 16.

Reset type: SYSRSn

16-0PMAXR0hPost Processing Block 3 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is larger.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information).

Reset type: SYSRSn

24.16.3.134 ADCPPB3PMAXI Register (Offset = 250h) [Reset = 0000h]

ADCPPB3PMAXI is shown in Figure 24-237 and described in Table 24-215.

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ADC PPB3 Partial Max Index Register

Figure 24-237 ADCPPB3PMAXI Register
15141312111098
RESERVEDPMAXI
R-0hR-0h
76543210
PMAXI
R-0h
Table 24-215 ADCPPB3PMAXI Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PMAXIR0hPost Processing Block 3 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information).

Reset type: SYSRSn

24.16.3.135 ADCPPB3PMIN Register (Offset = 254h) [Reset = 00000000h]

ADCPPB3PMIN is shown in Figure 24-238 and described in Table 24-216.

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ADC PPB3 Partial MIN Register

Figure 24-238 ADCPPB3PMIN Register
313029282726252423222120191817161514131211109876543210
SIGNPMIN
R-0hR-0h
Table 24-216 ADCPPB3PMIN Register Field Descriptions
BitFieldTypeResetDescription
31-17SIGNR0hSign Extended Bits. These bits reflect the same value as bit 16.

Reset type: SYSRSn

16-0PMINR0hPost Processing Block 3 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT the result replaces this register if it is smaller.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information).

Reset type: SYSRSn

24.16.3.136 ADCPPB3PMINI Register (Offset = 258h) [Reset = 0000h]

ADCPPB3PMINI is shown in Figure 24-239 and described in Table 24-217.

Return to the Summary Table.

ADC PPB3 Partial Min Index Register

Figure 24-239 ADCPPB3PMINI Register
15141312111098
RESERVEDPMINI
R-0hR-0h
76543210
PMINI
R-0h
Table 24-217 ADCPPB3PMINI Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PMINIR0hPost Processing Block 3 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB3RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB3 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB3RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB3RESULT timing information).

Reset type: SYSRSn

24.16.3.137 ADCPPB3TRIPLO2 Register (Offset = 25Ch) [Reset = 00000000h]

ADCPPB3TRIPLO2 is shown in Figure 24-240 and described in Table 24-218.

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ADC PPB3 Extended Trip Low Register

Figure 24-240 ADCPPB3TRIPLO2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITLO
R-0hR/W-0h
Table 24-218 ADCPPB3TRIPLO2 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0LIMITLOR/W0hADC Post Processing Block 3 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB3TRIPLO.LIMITLO2EN = 1.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPLO2[23:17] will be ignored in 16 bit mode
- TRIPLO2[23:13] will be ignored in 12 bit mode

Reset type: SYSRSn

24.16.3.138 ADCPPB4LIMIT Register (Offset = 270h) [Reset = 0000h]

ADCPPB4LIMIT is shown in Figure 24-241 and described in Table 24-219.

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ADC PPB4Conversion Count Limit Register

Figure 24-241 ADCPPB4LIMIT Register
15141312111098
RESERVEDLIMIT
R-0hR/W-0h
76543210
LIMIT
R/W-0h
Table 24-219 ADCPPB4LIMIT Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0LIMITR/W0hPost Processing Block 4 Oversampling Limit. Defines the number of conversions to accumulate before PSUM is automatically loaded into SUM.

To prevent PSUM from overflowing, do not write a value larger than 128 when the ADC is operating in 16-bit mode.

Reset type: SYSRSn

24.16.3.139 ADCPPBP4PCOUNT Register (Offset = 274h) [Reset = 0000h]

ADCPPBP4PCOUNT is shown in Figure 24-242 and described in Table 24-220.

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ADC PPB4 Partial Conversion Count Register

Figure 24-242 ADCPPBP4PCOUNT Register
15141312111098
RESERVEDPCOUNT
R-0hR-0h
76543210
PCOUNT
R-0h
Table 24-220 ADCPPBP4PCOUNT Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PCOUNTR0hPost Processing Block 4 Oversampling Partial Count. Each time a new result propagates through the PPB signal chain and accumulates into ADCPPB4PSUM this register is incremented by 1.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information).

Reset type: SYSRSn

24.16.3.140 ADCPPB4CONFIG2 Register (Offset = 278h) [Reset = 0000h]

ADCPPB4CONFIG2 is shown in Figure 24-243 and described in Table 24-221.

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ADC PPB4 Sum Shift Register

Figure 24-243 ADCPPB4CONFIG2 Register
15141312111098
COMPSELRESERVEDOSINTSELSWSYNCRESERVEDSYNCINSEL
R/W-0hR-0hR/W-0hR-0/W1S-0hR-0hR/W-0h
76543210
SYNCINSELSHIFT
R/W-0hR/W-0h
Table 24-221 ADCPPB4CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
15-14COMPSELR/W0hPost Processing Block 4 Compare Source Select. This field determines whether ADCPPB4RESULT, ADCPPB4PSUM, or ADCPPB4SUM is used for the zero-crossing detect logic and threshold compare.

00 = ADCPPB4RESULT is used for compare logic
01 = ADCPPB4PSUM is used for compare logic
10 = ADCPPB4SUM is used for compare logic
11 = Reserved

Note: when ADCPPB4PSUM is selected as the compare source and when a LIMIT match occurs (ADCPPB4LIMIT equals ADCPPB4COUNT) the ADCPPB4PSUM register will be cleared and the final sum will be loaded into ADCPPB4SUM. For this sample, the final sum, ADCPPB4SUM will be used for the compariosn instead of ADCPPB4PSUM.

Reset type: SYSRSn

13RESERVEDR0hReserved
12OSINTSELR/W0hPost Processing Block 4 Interrupt Source Select.

OSINT4 can be used to trigger an ADC interrupt (ADCINT1 through ADCINT4) via selection in the ADCINT1N2 or ADCINT3N4. This selection determines if a sync. event can trigger OSINT4 in addition to a PCOUNT = LIMIT event.

0 = OSINT4 will be generated from PCOUNT = LIMIT only
1 = OSTIN4 will be generated form PCOUNT = LIMIT or a sync. event.

Note: If a SYNC event would cause an OSINT one cycle after OSINT would have been cause by PCOUNT = LIMIT match, then the second OSINT is ignored.

Reset type: SYSRSn

11SWSYNCR-0/W1S0hPPB 4 software force sync. On a sync. event, all partial registers transfer to the final registers and are then reset.

Note: In the case where the software force occurs at the same time that a new sample is added to the PSUM and the PSUM is being used for a high or low limit compare, then the comparison will not occur.

Reset type: SYSRSn

10RESERVEDR0hReserved
9-4SYNCINSELR/W0hPPB 4 sync. input select. On a sync. event, all partial registers transfer to the final registers and are then reset.
Refer to SOC spec for details

Reset type: SYSRSn

3-0SHIFTR/W0hPost Processing Block 4 right shift. Defines the number of bits to right shift PSUM before loading into the final SUM.

0 : no right shift
1 : SUM = PSUM >> 1
2 : SUM = PSUM >> 2
...
10 : SUM = PSUM >> 10
11 - 15 : Reserved

Reset type: SYSRSn

24.16.3.141 ADCPPB4PSUM Register (Offset = 27Ch) [Reset = 00000000h]

ADCPPB4PSUM is shown in Figure 24-244 and described in Table 24-222.

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ADC PPB4 Partial Sum Register

Figure 24-244 ADCPPB4PSUM Register
313029282726252423222120191817161514131211109876543210
SIGNPSUM
R-0hR-0h
Table 24-222 ADCPPB4PSUM Register Field Descriptions
BitFieldTypeResetDescription
31-24SIGNR0hSign Extended Bits. These bits reflect the same value as bit 23.

Reset type: SYSRSn

23-0PSUMR0hPost Processing Block 4 Oversampling Partial Sum. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result is subsequently accumulated into this register.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC. In the case of multiple PPBs associated with the same SOC, the lowest numbered PPB's result will be availble 2 SYSCLK cycle after the associated ADCRESULT and subsequent results (in order from lowest numbered PPB to highest) will each become available every 2-3 SYSCLK cycles (refer to the TRM for detailed timing information).

Reset type: SYSRSn

24.16.3.142 ADCPPB4PMAX Register (Offset = 280h) [Reset = 00000000h]

ADCPPB4PMAX is shown in Figure 24-245 and described in Table 24-223.

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ADC PPB4 Partial Max Register

Figure 24-245 ADCPPB4PMAX Register
313029282726252423222120191817161514131211109876543210
SIGNPMAX
R-0hR-0h
Table 24-223 ADCPPB4PMAX Register Field Descriptions
BitFieldTypeResetDescription
31-17SIGNR0hSign Extended Bits. These bits reflect the same value as bit 16.

Reset type: SYSRSn

16-0PMAXR0hPost Processing Block 4 Oversampling Partial Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is larger.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information).

Reset type: SYSRSn

24.16.3.143 ADCPPB4PMAXI Register (Offset = 284h) [Reset = 0000h]

ADCPPB4PMAXI is shown in Figure 24-246 and described in Table 24-224.

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ADC PPB4 Partial Max Index Register

Figure 24-246 ADCPPB4PMAXI Register
15141312111098
RESERVEDPMAXI
R-0hR-0h
76543210
PMAXI
R-0h
Table 24-224 ADCPPB4PMAXI Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PMAXIR0hPost Processing Block 4 Oversampling Partial Index of Max. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMAX this register is loaded with the current value of PCOUNT.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information).

Reset type: SYSRSn

24.16.3.144 ADCPPB4PMIN Register (Offset = 288h) [Reset = 00000000h]

ADCPPB4PMIN is shown in Figure 24-247 and described in Table 24-225.

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ADC PPB4 Partial MIN Register

Figure 24-247 ADCPPB4PMIN Register
313029282726252423222120191817161514131211109876543210
SIGNPMIN
R-0hR-0h
Table 24-225 ADCPPB4PMIN Register Field Descriptions
BitFieldTypeResetDescription
31-17SIGNR0hSign Extended Bits. These bits reflect the same value as bit 16.

Reset type: SYSRSn

16-0PMINR0hPost Processing Block 4 Oversampling Partial Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT the result replaces this register if it is smaller.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information).

Reset type: SYSRSn

24.16.3.145 ADCPPB4PMINI Register (Offset = 28Ch) [Reset = 0000h]

ADCPPB4PMINI is shown in Figure 24-248 and described in Table 24-226.

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ADC PPB4 Partial Min Index Register

Figure 24-248 ADCPPB4PMINI Register
15141312111098
RESERVEDPMINI
R-0hR-0h
76543210
PMINI
R-0h
Table 24-226 ADCPPB4PMINI Register Field Descriptions
BitFieldTypeResetDescription
15-10RESERVEDR0hReserved
9-0PMINIR0hPost Processing Block 4 Oversampling Partial Index of Min. Each time a new result propagates through the PPB signal chain and latches into ADCPPB4RESULT if the result replaces PMIN this register is loaded with the current value of PCOUNT.

This register is reset when either a count-match event occurs (PCOUNT = LIMIT) or PPB4 receives a sync. event.

This result is available 1 SYSCLK cycle after the associated ADCPPB4RESULT is available. This will be 2 SYSCLK cycles after the associated ADCRESULT is available, unless multiple PPBs point to the same SOC (refer to the ADCPPB4RESULT timing information).

Reset type: SYSRSn

24.16.3.146 ADCPPB4TRIPLO2 Register (Offset = 290h) [Reset = 00000000h]

ADCPPB4TRIPLO2 is shown in Figure 24-249 and described in Table 24-227.

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ADC PPB4 Extended Trip Low Register

Figure 24-249 ADCPPB4TRIPLO2 Register
313029282726252423222120191817161514131211109876543210
RESERVEDLIMITLO
R-0hR/W-0h
Table 24-227 ADCPPB4TRIPLO2 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0LIMITLOR/W0hADC Post Processing Block 4 Trip High Low Limit. This value sets the digital comparator trip low limit if ADCPPB4TRIPLO.LIMITLO2EN = 1.

When comparing to an ADCPPBxRESULT register, the upper bits will be ignored:
- TRIPLO2[23:17] will be ignored in 16 bit mode
- TRIPLO2[23:13] will be ignored in 12 bit mode

Reset type: SYSRSn