SLAAEG4B October   2023  – July 2025 MSPM0C1104 , MSPM0C1105 , MSPM0C1106 , MSPM0H3216 , MSPM0L1306

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM0C Hardware Design Check List
  5. 2 Power Supplies in MSPM0C Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
      1. 3.2.1 Power-On Reset (POR) Monitor
      2. 3.2.2 Brownout Reset (BOR) Monitor
      3. 3.2.3 POR and BOR Behavior During Supply Changes
  7. 4 Clock System
    1. 4.1 Internal Oscillators
      1. 4.1.1 Internal Low-Frequency Oscillator (LFOSC)
      2. 4.1.2 Internal System Oscillator (SYSOSC)
    2. 4.2 External Oscillators & External Clock Input
      1. 4.2.1 Low-Frequency Crystal Oscillator (LFXT)
      2. 4.2.2 LFCLK_IN (Digital Clock)
      3. 4.2.3 High-Frequency Crystal Oscillator (HFXT)
      4. 4.2.4 HFCLK_IN (Digital Clock)
    3. 4.3 External Clock Output (CLK_OUT)
    4. 4.4 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug Port Pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
      1. 5.2.1 Standard XDS110
      2. 5.2.2 Lite XDS110 (MSPM0 LaunchPad™ kit)
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 COMP and DAC Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 I2C and SPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 Open-Drain GPIOs Enable 5V Communication Without a Level Shifter
    4. 8.4 Communicate With 1.8V Devices Without a Level Shifter
    5. 8.5 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
      1. 9.2.1 What is Ground Noise?
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
  14. 11Summary
  15. 12References
  16. 13Revision History

2.2 Analog Power Supply

Analog Mux VBOOST

In MSPM0C1105 and MSPM0C1106 which support COMP, the VBOOST circuit in the PMU generates an internal VBOOST supply that is used by the analog mux in COMP. The VBOOST circuit enables consistent analog mux performance across the external supply voltage (VDD) range.

Enabling and Disabling VBOOST

In MSPM0C1105 and MSPM0C1106, SYSCTL automatically manages the enable request for the VBOOST circuit based on the following parameters:

  1. The COMP peripheral PWREN settings.
  2. The MODE setting of any COMP which is enabled (FAST vs. ULP mode).
  3. The ANACPUMPCFG control bits in the GENCLKCFG register in SYSCTL.

VBOOST is disabled by default following a SYSRST. Use the application software to enable the VBOOST circuit before using the COMP. When a COMP is enabled by application software, SYSCTL also enables the VBOOST circuit to support the analog peripheral.

The VBOOST circuit has a startup time requirement (12µs typical) to transition from a disabled state to an enabled state. In the event that the startup time of the COMP is less than the VBOOST startup time, the peripheral startup time is extended to account for the VBOOST startup time.

Bandgap Voltage Reference

The PMU provides a temperature and supply voltage stable bandgap voltage reference which is used by the device for internal functions, including:

  • Driving the brownout reset circuit thresholds.
  • Supporting the core regulator.
  • Driving the on-chip VREF levels for on-chip analog peripherals.

The bandgap reference is enabled in RUN, SLEEP, and STOP modes. Bandgap voltage operates in a sampled mode in STANDBY to reduce power consumption, and is disabled in SHUTDOWN mode. SYSCTL manages the bandgap state automatically, no user configuration is required.