SLAAEG4B October   2023  – July 2025 MSPM0C1104 , MSPM0C1105 , MSPM0C1106 , MSPM0H3216 , MSPM0L1306

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 MSPM0C Hardware Design Check List
  5. 2 Power Supplies in MSPM0C Devices
    1. 2.1 Digital Power Supply
    2. 2.2 Analog Power Supply
    3. 2.3 Built-in Power Supply and Voltage Reference
    4. 2.4 Recommended Decoupling Circuit for Power Supply
  6. 3 Reset and Power Supply Supervisor
    1. 3.1 Digital Power Supply
    2. 3.2 Power Supply Supervisor
      1. 3.2.1 Power-On Reset (POR) Monitor
      2. 3.2.2 Brownout Reset (BOR) Monitor
      3. 3.2.3 POR and BOR Behavior During Supply Changes
  7. 4 Clock System
    1. 4.1 Internal Oscillators
      1. 4.1.1 Internal Low-Frequency Oscillator (LFOSC)
      2. 4.1.2 Internal System Oscillator (SYSOSC)
    2. 4.2 External Oscillators & External Clock Input
      1. 4.2.1 Low-Frequency Crystal Oscillator (LFXT)
      2. 4.2.2 LFCLK_IN (Digital Clock)
      3. 4.2.3 High-Frequency Crystal Oscillator (HFXT)
      4. 4.2.4 HFCLK_IN (Digital Clock)
    3. 4.3 External Clock Output (CLK_OUT)
    4. 4.4 Frequency Clock Counter (FCC)
  8. 5 Debugger
    1. 5.1 Debug Port Pins and Pinout
    2. 5.2 Debug Port Connection With Standard JTAG Connector
      1. 5.2.1 Standard XDS110
      2. 5.2.2 Lite XDS110 (MSPM0 LaunchPad™ kit)
  9. 6 Key Analog Peripherals
    1. 6.1 ADC Design Considerations
    2. 6.2 COMP and DAC Design Considerations
  10. 7 Key Digital Peripherals
    1. 7.1 Timer Resources and Design Considerations
    2. 7.2 UART and LIN Resources and Design Considerations
    3. 7.3 I2C and SPI Design Considerations
  11. 8 GPIOs
    1. 8.1 GPIO Output Switching Speed and Load Capacitance
    2. 8.2 GPIO Current Sink and Source
    3. 8.3 Open-Drain GPIOs Enable 5V Communication Without a Level Shifter
    4. 8.4 Communicate With 1.8V Devices Without a Level Shifter
    5. 8.5 Unused Pins Connection
  12. 9 Layout Guides
    1. 9.1 Power Supply Layout
    2. 9.2 Considerations for Ground Layout
      1. 9.2.1 What is Ground Noise?
    3. 9.3 Traces, Vias, and Other PCB Components
    4. 9.4 How to Select Board Layers and Recommended Stack-up
  13. 10Bootloader
  14. 11Summary
  15. 12References
  16. 13Revision History

7.3 I2C and SPI Design Considerations

SPI and I2C protocols are widely used in communication between devices or boards, such as data exchange between an MCU and a sensor. MSPM0C1103 and MSPM0C1104 include up to 12MHz high-speed SPI, and MSPM0C1105 and MSPM0C1106 include up to 16MHz high-speed SPI. The SPI supports 3wire, 4wire, chip select, and command mode. To design a system based on the requirements, see Figure 7-4.

Some SPI peripheral devices need PICO (Peripherals Input Controller Output) keep high logic. In this case, add a pullup resistor to PICO pin.

External Connections for Different SPI Configurations Figure 7-4 External Connections for Different SPI Configurations

For I2C bus, the MSPM0C device supports standard, fast and fast plus mode, as shown in Table 7-4.

External pullup resistors are required when using I2C bus. The value of these resistors depends on the I2C speed; TI recommends 2.2k to support Fast mode+. For systems concerned with power consumption, large resistor values can be used. ODIO (see Section 8) can be used to implement communication with a 5V device.

Table 7-4 MSPM0C I2C Characteristics
PARAMETERS TEST CONDITIONS Standard Mode Fast Mode Fast Mode Plus UNIT
MIN MAX MIN MAX MIN MAX
fI2C I2C input clock frequency I2C in Power Domain0 MSPM0C1103 and MSPM0C1104 24 24 24 MHz
MSPM0C1105 and MSPM0C1106 2 32 8 32 20 32
fSCL SCL clock frequency 100K 400K 1M Hz
tHD,STA Hold time (repeated) START 4 0.6 0.26 us
tLOW Low period of the SCL clock 4.7 1.3 0.5 us
tHIGH High period of the SCL clock 4 0.6 0.26 us
tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us
tHD,DAT Data hold time 0 0 0 us
tSU,DAT Data setup time 250 100 50 us
tSU,STO Setup time for STOP 4 0.6 0.26 us
tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us
tVD;DAT Data valid time 3.45 0.9 0.45 us
tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us
Typical I2C Bus Connection Figure 7-5 Typical I2C Bus Connection