SLASFM6 October   2026 TAS2573

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Software Power Modes Control and Software Reset
        3. 6.3.1.3 Efficiency and power saving modes
          1. 6.3.1.3.1 Noise Gate
          2. 6.3.1.3.2 Music Efficiency Mode
          3. 6.3.1.3.3 VDD Y-bridge
          4. 6.3.1.3.4 Class-H Boost
        4. 6.3.1.4 2S Battery Mode
        5. 6.3.1.5 Low voltage battery mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Signal Processor
          1. 6.4.2.1.1 Algorithm Blocks
          2. 6.4.2.1.2 Algorithm Features
          3. 6.4.2.1.3 Factory Calibration
        2. 6.4.2.2 Digital Volume Control and Amplifier Output Level
        3. 6.4.2.3 High Pass Filter
        4. 6.4.2.4 Class-D Amplifier
        5. 6.4.2.5 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.5.1 Voltage Limiter and Clipping protection
        6. 6.4.2.6 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
      4. 6.4.4 Boost
      5. 6.4.5 Speaker current and voltage (IV) sensing
      6. 6.4.6 Supply Voltage Monitors
      7. 6.4.7 Thermal Protection
      8. 6.4.8 Clocks and PLL
        1. 6.4.8.1 Auto clock based wakeup and clock errors
      9. 6.4.9 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE_0 Registers
    2. 7.2 PAGE_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

6.4.8.1 Auto clock based wakeup and clock errors

TAS2573 supports flexible operating mode transition from active to shutdown and vice-verse using ASI clock auto detection feature. When MODE[1:0] is configured as '11' the device toggles between Active and Software shutdown state based on valid ASI clock signals applied on the ASI input pins, for example BCLK and FSYNC. If no ASI clocks are detected in this mode, the device remains in software shutdown, with software shutdown mode IQ on VDD pin, until a valid BCLK and FSYNC clock is detected. Once a valid clock is detected, the device is powered up in active state until the clocks are valid or device is shutdown using software or hardware shutdown commands.

The device can detect and raise interrupt flags on detection of incorrect clock configurations based on status of CLK_ERR_PWR_EN. When this bit is set high, the device monitors for activity on the clock pins and flags any error using the latched interrupts status register. The device can also raise interrupts using IRQZ pin based on status of the corresponding interrupt MASK registers. When the error protection bit is enabled, if a clock error is detected, the device automatically shuts-down with proper shutdown sequencing and minimize any clicks and pops due to invalid clocks.

When the device is in shutdown state, the clock error detection can be delayed to provide system with time required to settle the input clocks. This power up delay in clock error detection is controlled using an internal pre-power up clock error detection timer configured by CLK_HALT_TIMER. If device does not detect a valid clock at the end of the CLK_HALT_TIMER expiry, the Pre-Power-up Clock error is flagged on INT_LTCH4[2] bit, and corresponding interrupt can be generated on IRQZ pin based on status of INT_MASK4[2] bit. When MODE[1:0] is configured as '11' (Wake-up on ASI mode), CLK_HALT_TIMER of '000' is not recommended and the device is stopped from entering the software shutdown and increases the VDD IQ while the device is shutdown.

Once the device is powered up, the external and internally generated clocks are constantly monitored based on status of CLK_ERR_PWR_EN bit. If enabled, any error in external or internal clock is flagged using the clock error status register INT_LTCH2[3] bit, and corresponding interrupt can be generated on IRQZ pin based on status of INT_MASK2[3].

For system flexibility, the device also sets the error status for the type of detected clock error. The device can also be configured to raise an interrupt on IRQZ pin for any specific type of clock error, instead of using the generic clock error interrupt generation. Table 6-43 below explains the different type of clock errors and corresponding status bits and interrupt MASK register bits. One or more register bits in the table below can be set based on the type of clock error detected.

If the device shuts down due to any type of clock error, the device can attempt to re-power automatically when MODE[1:0] is set to '11'.

Table 6-41 Clock Error Detection Control
CLK_ERR_PWR_ENSetting
0Disabled
1Enabled (default)
Table 6-42 Clock Halt Timer
CLK_HALT_TIMER[2:0]Setting
000Disabled (infinite time).
0010.8ms (default)
0103.2ms
01134.1ms
10068.3ms
101256ms
110768ms
1111.3s
Table 6-43 Clock error type description
Clock error typeDescriptionStatus flag register bitIRQZ generation Mask bit
Clock errorClock error for any internal or external clocking configuration errors. This bit is set along with specific clock errors detected in the rest of the table below except for Pre-Power-up Clock errors. INT_LTCH2[3]INT_MASK2[3]
Pre-Power-up Clock errorClock error detected during shutdown mode after clock error is detected at end of CLK_HALT_TIMER. INT_LTCH4[2]INT_MASK4[2]
Clock ratio change errorClock error detected due to easily change in FSYNC to SBCLK ratio. INT_LTCH2[2]INT_MASK2[2]
Fs change errorClock error detected due to easily change in FSYNC clock frequencyINT_LTCH2[1]INT_MASK2[1]
Fs invalid errorClock error detected due to incorrect FSYNC clock frequencyINT_LTCH2[0]INT_MASK2[0]
Frame out of syncClock error detected due to Frame out of syncINT_LTCH2[5]INT_MASK2[5]
Internal PLL Clock errorClock error detected due to internally generated clock frequency error. INT_LTCH2[4]INT_MASK2[4]

The device also has a digital watchdog timer which monitors for errors in the internal digital state machine and shuts down the device on detection of such errors. This error can also raise an interrupt on IRQZ pin and flag to the host device of the error state.