SLASFM6 October   2026 TAS2573

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Software Power Modes Control and Software Reset
        3. 6.3.1.3 Efficiency and power saving modes
          1. 6.3.1.3.1 Noise Gate
          2. 6.3.1.3.2 Music Efficiency Mode
          3. 6.3.1.3.3 VDD Y-bridge
          4. 6.3.1.3.4 Class-H Boost
        4. 6.3.1.4 2S Battery Mode
        5. 6.3.1.5 Low voltage battery mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePathâ„¢ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Signal Processor
          1. 6.4.2.1.1 Algorithm Blocks
          2. 6.4.2.1.2 Algorithm Features
          3. 6.4.2.1.3 Factory Calibration
        2. 6.4.2.2 Digital Volume Control and Amplifier Output Level
        3. 6.4.2.3 High Pass Filter
        4. 6.4.2.4 Class-D Amplifier
        5. 6.4.2.5 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.5.1 Voltage Limiter and Clipping protection
        6. 6.4.2.6 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
      4. 6.4.4 Boost
      5. 6.4.5 Speaker current and voltage (IV) sensing
      6. 6.4.6 Supply Voltage Monitors
      7. 6.4.7 Thermal Protection
      8. 6.4.8 Clocks and PLL
        1. 6.4.8.1 Auto clock based wakeup and clock errors
      9. 6.4.9 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE_0 Registers
    2. 7.2 PAGE_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

Software Power Modes Control and Software Reset

The TAS2573 power state can be controlled using the register MODE[1:0]. Change in any of the MODE settings does not cause the device to lose any of the existing device configuration register settings.

Active state: When MODE[1:0] is configured as '00', the device enters an active mode of operation with the audio and the I-V sense channels powered up with proper power-up sequencing to minimize the click and pop. Speaker voltage and current sensing are operational if enabled.

Mute state: When MODE[1:0] is configured as '01', the device enters mute mode of operation. If the state of the device is software shutdown before the mute state is programmed, the audio and the I-V sense channels powers up with proper power-up sequencing to minimize the click and pop and then the channels enter into mute mode. If the audio channel is active when the mute state is asserted, the device volume ramps down the Class-D amplifier to a mute state. During mute the Class-D still switches, but transmits no audio content. If mute is de-asserted and the device is configured into an active state, the device volume ramps back to the programmed digital volume setting.

Software shutdown state: When MODE[1:0] is configured as '10', the device enters software shutdown mode. This mode powers down all analog blocks required to playback audio but does not cause the device to lose register state. If audio is playing when Software Shutdown is asserted, the Class-D volume ramps down before shutting down. When de-asserted, the Class-D begins switching and volume ramp back to the programmed digital volume setting.

Clock based Active and shutdown state: When MODE[1:0] is configured as '11' the device toggles between Active and Shutdown state based on valid ASI clock signals applied on the ASI input pins, BCLK and FSYNC. When clocks are applied, the device automatically detects the clock signals and follow proper power-up sequencing to avoid any power-up click and pop. When the audio channels are powered up and the ASI clock is removed, the device automatically starts power-down sequencing and avoid any click and pop. TI recommends to do a volume ramp-down in the input data stream before stopping the clocks for the best pop & click experience (device software mute mode can be used to realize this).

Table 6-2 Software Mode Control
MODE[1:0] Configuration
00 Device in active mode of operation
01 Reserved
10 (default) Device in software shutdown mode
11 Device in Clock based Active and shutdown mode

TAS2573 can be reset to the default configuration by setting the SW_RESET register to '1'. If the device is powered up, when the SW_RESET bit is set high, all the channels are powered down immediately. All the registers are restored to the default state when SW_RESET is set high. This bit is self-clearing and goes back to '0' once the reset is complete.

The device can also signal to the host once the status of the device reaches Active mode of operation using the INT_LTCH0[1] bit (Section 6.3.2). This bit is a live device status bit and reflects the device status in real-time. This bit is set high when the device is in Active mode and set low when the device is in shutdown mode.