SLASFM6 Data sheet

Table 7-1 lists the memory-mapped registers for the PAGE_0 registers. All register offset addresses not listed in Table 7-1 must be considered as reserved locations and the register contents must not be modified.

Table 7-1 PAGE_0 Registers

Offset	Acronym	Register Name	Section
0h	Page	Device Page	Section 7.1.1
1h	SW_RESET	Software Reset	Section 7.1.2
2h	PWR_CTL	Power Control	Section 7.1.3
3h	DEVICE_CFG_01	Device configuration registers	Section 7.1.4
4h	DEVICE_CFG_02	Device configuration registers	Section 7.1.5
5h	DEVICE_CFG_03	Device configuration registers	Section 7.1.6
6h	DEVICE_CFG_04	Device configuration registers	Section 7.1.7
7h	DEVICE_CFG_05	Device configuration registers	Section 7.1.8
8h	TDM_CFG1	TDM Configuration registers	Section 7.1.9
9h	TDM_CFG2	TDM Configuration registers	Section 7.1.10
Ah	TDM_CFG3	TDM Configuration registers	Section 7.1.11
Ch	TDM_CFG5	TDM Configuration registers	Section 7.1.12
Dh	TDM_CFG6	TDM Configuration registers	Section 7.1.13
Eh	TDM_CFG7	TDM Configuration registers	Section 7.1.14
Fh	TDM_CFG8	TDM Configuration registers	Section 7.1.15
10h	TDM_CFG9	TDM Configuration registers	Section 7.1.16
11h	TDM_CFG10	TDM Configuration registers	Section 7.1.17
12h	TDM_CFG11	TDM Configuration registers	Section 7.1.18
13h	TDM_CFG12	TDM Configuration registers	Section 7.1.19
14h	TDM_DET	TDM Clock detection monitor	Section 7.1.20
15h	MONITOR_CFG_01	Monitoring Configuration	Section 7.1.21
16h	MONITOR_CFG_02	Monitoring Configuration	Section 7.1.22
17h	LIM_CFG_0	Limiter configuration	Section 7.1.23
18h	BOP_CFG_0	Brown out protection configuration	Section 7.1.24
19h	TONE_GEN_01	Internal tone generator	Section 7.1.25
1Ah	TONE_GEN_02	Internal tone generator	Section 7.1.26
1Bh	IO_CFG_01	IO Configuration	Section 7.1.27
1Ch	IO_CFG_02	IO Configuration	Section 7.1.28
1Dh	IO_CFG_03	IO Configuration	Section 7.1.29
1Eh	NG_CFG0	Noise Gate Controls	Section 7.1.30
21h	BST_CFG_01	Boost Configuration	Section 7.1.31
22h	BST_CFG_02	Boost Configuration	Section 7.1.32
25h	INTERRUPT_CFG1	IRQZ clear	Section 7.1.33
2Ch	TDM_CFG13	TDM Configuration registers	Section 7.1.34
2Eh	TDM_CFG15	TDM Configuration registers	Section 7.1.35
31h	CLASSD_CFG_01	Class	Section 7.1.36
32h	CLASSD_CFG_02	Class	Section 7.1.37
3Bh	BST_CFG_05	Boost Configuration	Section 7.1.38
3Ch	THERM_CFG	Thermal warning configuration	Section 7.1.39
5Bh	INT_MASK_0	Interrupt Masks	Section 7.1.40
5Ch	INT_MASK_1	Interrupt Masks	Section 7.1.41
5Dh	INT_MASK_2	Interrupt Masks	Section 7.1.42
5Fh	INT_MASK_3	Interrupt Masks	Section 7.1.43
60h	INT_LATCH_0	Latched interrupt readback	Section 7.1.44
61h	INT_LATCH_1	Latched interrupt readback	Section 7.1.45
62h	INT_LATCH_2	Latched interrupt readback	Section 7.1.46
63h	INT_LATCH_3	Latched interrupt readback	Section 7.1.47
64h	INT_LATCH_4	Latched interrupt readback	Section 7.1.48
65h	NG_IDLE_STATUS	Latched interrupt readback	Section 7.1.49
66h	INT_MASK_5	Interrupt Masks	Section 7.1.50
67h	INT_LATCH_5	Latched interrupt readback	Section 7.1.51
78h	REV_ID	Revision and PG ID	Section 7.1.52
7Fh	BOOK	Device Book	Section 7.1.53

7.1.1 Page Register (Offset = 0h) [Reset = 00h]

Page is shown in Table 7-2.

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The device's memory map is divided into pages and books. This register sets the page.

Table 7-2 Page Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	PAGE	R/W	0h	Sets the device page. 00h = Page 0 01h = Page 1 FFh = Page 255

7.1.2 SW_RESET Register (Offset = 1h) [Reset = 00h]

SW_RESET is shown in Table 7-3.

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Asserting Software Reset places all register values in the default POR (Power on Reset) state.

Table 7-3 SW_RESET Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0h	RESERVED
0	SW_RESET	R/W	0h	Software reset. Bit is self clearing. 0h = Don't reset 1h = Reset

7.1.3 PWR_CTL Register (Offset = 2h) [Reset = 02h]

PWR_CTL is shown in Table 7-4.

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Sets device's mode of operation and Power Configuration

Table 7-4 PWR_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	RESERVED
1-0	MODE	R/W	2h	Device operational mode. 0h = Active 1h = Mute 2h = Software Shutdown 3h = Wake-up and Shutdown on ASI Clock

7.1.4 DEVICE_CFG_01 Register (Offset = 3h) [Reset = C0h]

DEVICE_CFG_01 is shown in Table 7-5.

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This register configures the various device modes.

Table 7-5 DEVICE_CFG_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	EFFICIENCY_MODE	R/W	3h	Device operational mode. 0h = Music Efficiency and Noise Gate mode disabled 1h = Noise Gate Mode Only 2h = Music Efficiency Only 3h = Music Efficiency + Noise Gate mode
5-2	RESERVED	R	0h	RESERVED
1-0	SDZ_MODE	R/W	0h	SDZ Mode configuration. 0h = Soft shutdown and device reset 1h = Immediate shutdown and device reset 2h = Soft shutdown only (registers settings are not cleared) 3h = Reserved

7.1.5 DEVICE_CFG_02 Register (Offset = 4h) [Reset = 8Ch]

DEVICE_CFG_02 is shown in Table 7-6.

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This register configures the various device modes.

Table 7-6 DEVICE_CFG_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	I2C_GBL_EN	R/W	1h	I2C global address is 0h = Disabled 1h = Enabled
6	RESERVED	R	0h	Reserved
5-3	CLK_HALT_TIME	R/W	1h	Device aborts the clock check after the time out defined by this register 0h = Perpetual checking mode. ASI CLK check is never aborted 1h = 800 us 2h = 3.2ms 3h = 34.1ms 4h = 68.3ms 5h = 256ms 6h = 768ms 7h = 1.3s
2	CLK_BASED_PWR_UP	R/W	1h	Power up/down based on valid ASI clocks is 0h = Disable 1h = Enabled.
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.1.6 DEVICE_CFG_03 Register (Offset = 5h) [Reset = 00h]

DEVICE_CFG_03 is shown in Table 7-7.

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This register configures the various device modes.

Table 7-7 DEVICE_CFG_03 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	OCE_RETRY	R/W	0h	Retry after over current event. 0h = Do not retry 1h = Retry after "RETRY_WAIT_TIME"
4	OTE_RETRY	R/W	0h	Retry after over temperature event. 0h = Do not retry 1h = Retry after "RETRY_WAIT_TIME"
3	RESERVED	R	0h	Reserved
2	CLKE_RETRY	R/W	0h	Retry after Internal Clock Error event. 0h = Do not retry 1h = Retry after "RETRY_WAIT_TIME"
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.1.7 DEVICE_CFG_04 Register (Offset = 6h) [Reset = 04h]

DEVICE_CFG_04 is shown in Table 7-8.

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This register configures the various device modes.

Table 7-8 DEVICE_CFG_04 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	RESERVED
5-4	SEL_VBAT_MODE	R/W	0h	Selects VBAT mode of operation 0h = VBAT 1S mode, VBAT pin voltage monitored 1h = VBAT 1S mode, VBAT_SNS pin voltage monitored Ah = VBAT 2S mode, VBAT_SNS pin voltage monitored Bh = RESERVED
3-2	IRQZ_PIN_CFG	R/W	1h	IRQZ interrupt configuration. IRQZ asserts 0h = on any unmasked live interrupts 1h = on any unmasked latched interrupts 2h = for 2-4ms one time on any unmasked live interrupt event 3h = for 2-4ms every 4ms on any unmasked latched interrupts
1	RESERVED	R	0h	RESERVED
0	RETRY_WAIT_TIME	R/W	0h	Retry wait time after device detects error (Valid only for errors with retry options available) 0h = 1.5 sec 1h = 100ms

7.1.8 DEVICE_CFG_05 Register (Offset = 7h) [Reset = 00h]

DEVICE_CFG_05 is shown in Table 7-9.

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This register configures the various device modes.

Table 7-9 DEVICE_CFG_05 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6	SAMPLE_RATE_CFG	R/W	0h	Sampling Rate selection 0h = Audio data rate is multiple/sub-multiple of 48Ksps 1h = Audio data rate is multiple/sub-multiple of 44.1Ksps
5-0	AMP_LVL	R/W	0h	Device Channel Gain setting 0h = 21.000dB 1h = 20.498dB 2h = 19.997dB 3h = 19.495dB 4h = 18.993dB 26h = 1.935dB 27h = 1.434dB 28h = 0.932dB 29h = 0.430dB 2Ah = -0.071dB

7.1.9 TDM_CFG1 Register (Offset = 8h) [Reset = 82h]

TDM_CFG1 is shown in Table 7-10.

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This register configures device TDM modes

Table 7-10 TDM_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	FRAME_START	R/W	1h	TDM frame start polarity. 0h = Low to High on FSYNC 1h = High to Low on FSYNC
6	RX_JUSTIFY	R/W	0h	TDM RX sample justification within the time slot. 0h = Left 1h = Right
5-1	RX_OFFSET	R/W	1h	TDM RX start of frame to time slot 0 offset (SBCLK cycles).
0	RX_EDGE	R/W	0h	TDM RX capture clock polarity. 0h = Rising edge of SBCLK 1h = Falling edge of SBCLK

7.1.10 TDM_CFG2 Register (Offset = 9h) [Reset = 0Ah]

TDM_CFG2 is shown in Table 7-11.

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This register configures device TDM modes

Table 7-11 TDM_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	IVMON_SLEN	R/W	0h	Sets the current and voltage data to length of 0h = 16 bits 1h = 12 bits 2h = 8 bits 3h = RESERVED
5-4	RESERVED	R	0h	RESERVED
3-2	RX_WLEN	R/W	2h	TDM RX word length. 0h = 16-bits 1h = 20-bits 2h = 24-bits 3h = 32-bits
1-0	RX_SLEN	R/W	2h	TDM RX time slot length. 0h = 16-bits 1h = 24-bits 2h = 32-bits 3h = RESERVED

7.1.11 TDM_CFG3 Register (Offset = Ah) [Reset = 10h]

TDM_CFG3 is shown in Table 7-12.

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This register configures device TDM modes

Table 7-12 TDM_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RX_SLOT_R	R/W	1h	TDM RX Right Audio Channel Time Slot.
3-0	RX_SLOT_L	R/W	0h	TDM RX Left Audio Channel Time Slot.

7.1.12 TDM_CFG5 Register (Offset = Ch) [Reset = 13h]

TDM_CFG5 is shown in Table 7-13.

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This register configures device TDM modes

Table 7-13 TDM_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TX_KEEPCY	R/W	0h	TDM TX SDOUT LSB data is driven for 0h = full-cycle 1h = half-cycle
6	TX_KEEPLN	R/W	0h	TDM TX SDOUT holds the bus for the following when TX_KEEPEN is enabled 0h = 1LSB cycle 1h = always
5	TX_KEEPEN	R/W	0h	TDM TX SDOUT bus keeper enable. 0h = Disable bus keeper 1h = Enable bus keeper
4	TX_FILL	R/W	1h	TDM TX SDOUT unused bitfield fill. 0h = Transmit 0 1h = Transmit Hi-Z
3-1	TX_OFFSET	R/W	1h	TDM TX start of frame to time slot 0 offset.
0	TX_EDGE	R/W	1h	TDM TX launch clock polarity. 0h = Rising edge of SBCLK 1h = Falling edge of SBCLK

7.1.13 TDM_CFG6 Register (Offset = Dh) [Reset = 02h]

TDM_CFG6 is shown in Table 7-14.

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This register configures device TDM modes

Table 7-14 TDM_CFG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6	VSNS_TX	R/W	0h	TDM TX voltage sense transmit enable. 0h = Disabled 1h = Enabled
5-0	VSNS_SLOT	R/W	2h	TDM TX voltage sense time slot.

7.1.14 TDM_CFG7 Register (Offset = Eh) [Reset = 00h]

TDM_CFG7 is shown in Table 7-15.

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This register configures device TDM modes

Table 7-15 TDM_CFG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6	ISNS_TX	R/W	0h	TDM TX current sense transmit enable. 0h = Disabled 1h = Enabled
5-0	ISNS_SLOT	R/W	0h	TDM TX current sense time slot.

7.1.15 TDM_CFG8 Register (Offset = Fh) [Reset = 04h]

TDM_CFG8 is shown in Table 7-16.

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This register configures device TDM modes

Table 7-16 TDM_CFG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	VBAT_SLEN	R/W	0h	TDM TX VBAT time slot length. 0h = Truncate to 8-bits 1h = Left justify to 16-bits
6	VBAT_TX	R/W	0h	TDM TX VBAT transmit enable. 0h = Disabled 1h = Enabled
5-0	VBAT_SLOT	R/W	4h	TDM TX VBAT time slot.

7.1.16 TDM_CFG9 Register (Offset = 10h) [Reset = 05h]

TDM_CFG9 is shown in Table 7-17.

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This register configures device TDM modes

Table 7-17 TDM_CFG9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6	TEMP_TX	R/W	0h	TDM TX temp sensor transmit enable. 0h = Disabled 1h = Enabled
5-0	TEMP_SLOT	R/W	5h	TDM TX temp sensor time slot.

7.1.17 TDM_CFG10 Register (Offset = 11h) [Reset = 07h]

TDM_CFG10 is shown in Table 7-18.

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This register configures device TDM modes

Table 7-18 TDM_CFG10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6	STATUS_TX	R/W	0h	TDM TX status bits transmit enable. 0h = Disabled 1h = Enabled
5-0	STATUS_SLOT	R/W	7h	TDM TX status bits time slot.

7.1.18 TDM_CFG11 Register (Offset = 12h) [Reset = 06h]

TDM_CFG11 is shown in Table 7-19.

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This register configures device TDM modes

Table 7-19 TDM_CFG11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PVDD_SLEN	R/W	0h	TDM TX PVDD time slot length. 0h = Truncate to 8-bits 1h = Left justify to 16-bits
6	PVDD_TX	R/W	0h	TDM TX PVDD transmit enable. 0h = Disabled 1h = Enabled
5-0	PVDD_SLOT	R/W	6h	TDM TX PVDD time slot.

7.1.19 TDM_CFG12 Register (Offset = 13h) [Reset = 12h]

TDM_CFG12 is shown in Table 7-20.

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This register configures device TDM modes

Table 7-20 TDM_CFG12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	AUDIO_SLEN	R/W	0h	TDM audio slot length 0h = 16-bits 1h = 24-bits
6	AUDIO_TX	R/W	0h	TDM audio output transmit enable 0h = Disabled 1h = Enabled
5-0	AUDIO_SLOT	R/W	12h	TDM TX status time slot.

7.1.20 TDM_DET Register (Offset = 14h) [Reset = 7Fh]

TDM_DET is shown in Table 7-21.

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Readback of internal auto-rate detection.

Table 7-21 TDM_DET Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6-3	FS_RATIO_DETECTED	R	Fh	Detected SBCLK to FSYNC ratio. 00h = 16 01h = 24 02h = 32 03h = 48 04h = 64 05h = 96 06h = 128 07h = 192 08h = 256 09h = 384 0Ah = 512 0Bh = 125 0Dh = 500 0Eh = RESERVED 0Fh = Invalid ratio
2-0	FS_RATE_DETECTED	R	7h	Detected sample rate of TDM bus. 0h = RESERVED 1h = 14.7/16KHz 2h = 22.05/24KHz 3h = 29.4/32KHz 4h = 44.1/48KHz 5h = 88.2/96kHz 6h = 176.4/192kHz 7h = Error condition

7.1.21 MONITOR_CFG_01 Register (Offset = 15h) [Reset = 00h]

MONITOR_CFG_01 is shown in Table 7-22.

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This register configures the Monitor channels of the device

Table 7-22 MONITOR_CFG_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SUPPLY_SAMPLING_RATE	R/W	0h	Configure VBAT and PVDD sampling rates 0h = VBAT Sampling rate is higher than PVDD 1h = PVDD Sampling rate is higher than VBAT
6-0	RESERVED	R	0h	RESERVED

7.1.22 MONITOR_CFG_02 Register (Offset = 16h) [Reset = 30h]

MONITOR_CFG_02 is shown in Table 7-23.

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This register configures the Monitor channels of the device

Table 7-23 MONITOR_CFG_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IVSENSE_LPF_ENABLE	R/W	0h	Control for 6kHz LPF on the IV sense channel 0h = IV Sense LPF disabled 1h = IV sense LPF enabled
6-5	VSENSE_GAIN_SEL	R/W	1h	VSNS Full-scale (FS) programming
4-3	ISENSE_GAIN_SEL	R/W	2h	ISNS Full-scale (FS) programming
2-0	RESERVED	R	0h	RESERVED

7.1.23 LIM_CFG_0 Register (Offset = 17h) [Reset = 00h]

LIM_CFG_0 is shown in Table 7-24.

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This register configures the voltage limiter module

Table 7-24 LIM_CFG_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	LIM_MODE	R/W	0h	Limiter enable. 0h = Disabled 1h = VBAT voltage based limiter mode 2h = PVDD voltage based limiter mode 3h = ClassH Boost voltage based voltage limiter
5	SUPPLY_HEADROOM_LIM_MODE	R/W	0h	Select Limiter threshold based on supply headroom 0h = Disabled 1h = Enabled
4-0	RESERVED	R	0h	RESERVED

7.1.24 BOP_CFG_0 Register (Offset = 18h) [Reset = 00h]

BOP_CFG_0 is shown in Table 7-25.

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This register configures brown out protection module

Table 7-25 BOP_CFG_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R	0h	RESERVED
4	BOP_SRC	R/W	0h	Brown out prevention Source control 0h = VBAT 1h = PVDD
3	BOPSD_EN	R/W	0h	Brown out prevention shutdown enable. 0h = Disabled 1h = Enabled. Device shuts down when VBAT voltage is lower than programmed BOSD_THR_LVL[24:0]
2	BOP_HLD_CLR	R/W	0h	BOP infinite hold clear (self clearing). Available when BOP_INF_HLD = 1 0h = Don't clear 1h = Clear.
1	BOP_INF_HLD	R/W	0h	Infinite hold on brown out event. 0h = Use BOP_HLD_TM after brown out event 1h = Don't release until BOP_HLD_CLR is asserted high
0	BOP_EN	R/W	0h	Brown out prevention (BOP) enable. 0h = Disabled 1h = Enabled

7.1.25 TONE_GEN_01 Register (Offset = 19h) [Reset = 40h]

TONE_GEN_01 is shown in Table 7-26.

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Configurations for internal tone generator

Table 7-26 TONE_GEN_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INTERNAL_TONE_PLAYBACK_EN	R/W	0h	Pilot Tone signal playback control 0h = Pilot tone is not generated 1h = Pilot tone is generated (chirp_en must be set 0)
6	INTERNAL_TONE_MIXING_EN	R/W	1h	Internal tone mixing control 0h = Only tone is played(Audio data from ASI is ignored by FW) 1h = Tone signal is mixed with Audio data and played together
5	INTERNAL_TONE_CLK_SEL	R/W	0h	Clock source for tone generator 0h = External clocks 1h = Internal Oscillator
4	RESERVED	R	0h	Reserved
3-0	RESERVED	R	0h	RESERVED

7.1.26 TONE_GEN_02 Register (Offset = 1Ah) [Reset = 96h]

TONE_GEN_02 is shown in Table 7-27.

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Configurations for internal tone generator

Table 7-27 TONE_GEN_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	CHIRP_FREQ_CYCLES	R/W	9h	No of cycles of each frequency in the chirp. Next frequency is always at zero cross of previous frequency cycle. 0h = 1 Cycle 1h = 2 Cycles Fh = 16 Cycles
3	CHIRP_EN	R/W	0h	Chirp Tone playback Control (Dynamic reg) (Note: ASI must be active with valid clock and fsync. Audio data can be Zero) 0h = Chirp tone is not generated 1h = Chirp tone is generated (pilot_tone_en must be set 0)
2	INTERNAL_TONE_GEN_ENZ	R/W	1h	Disables internal tone generation feature (Need to reset this bit to use tone feature) 0h = Tone Generator enabled 1h = Tone Generator disabled
1	CHIRP_RAMP_EN	R/W	1h	Chirp Ramp Control 0h = Ramp up/down disabled 1h = Ramp up/down enabled
0	RESERVED	R	0h	RESERVED

7.1.27 IO_CFG_01 Register (Offset = 1Bh) [Reset = 01h]

IO_CFG_01 is shown in Table 7-28.

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This register configures the IO buffers

Table 7-28 IO_CFG_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	SDO_DRIVE_SEL	R/W	0h	Drive strength control register for SDO pad 0h = 2mA drive setting 1h = 4mA drive setting 2h = 6mA drive setting 3h = 8mA drive setting
5-4	IRQZ_DRIVE_SEL	R/W	0h	Drive strength control register for IRQZ pad 0h = 2mA drive setting 1h = 4mA drive setting 2h = 6mA drive setting 3h = 8mA drive setting
3-2	SDA_DRIVE_SEL	R/W	0h	Drive strength control register for SDA pad 0h = 2mA drive setting 1h = 4mA drive setting 2h = 6mA drive setting 3h = 8mA drive setting
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.1.28 IO_CFG_02 Register (Offset = 1Ch) [Reset = 3Ch]

IO_CFG_02 is shown in Table 7-29.

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This register configures the IO buffers

Table 7-29 IO_CFG_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	IRQZ_POL	R/W	0h	IRQZ pin polarity for interrupt. 0h = Active low 1h = Active High
6	IRQZ_PU	R/W	0h	IRQZ internal pull/dn up enable. 0h = pull-up/dn disabled 1h = pull-up/dn enabled as per irqz_pol
5	EN_SDO_OUTPUT	R/W	1h	SDO (ASI) O/P Stage Enable 0h = SDO O/P Stage is disabled during function mode (Tristated) 1h = Enabled during function mode
4	EN_ASI2_SDO_OUTPUT	R/W	1h	SDO (ASI) O/P Stage Enable 0h = SDO O/P Stage is disabled during function mode (Tristated) 1h = Enabled during function mode
3	EN_ASI2_SBCLK_OUTPUT	R/W	1h	SDO (ASI) O/P Stage Enable 0h = SDO O/P Stage is disabled during function mode (Tristated) 1h = Enabled during function mode
2	EN_ASI2_FSYNC_OUTPUT	R/W	1h	SDO (ASI) O/P Stage Enable 0h = SDO O/P Stage is disabled during function mode (Tristated) 1h = Enabled during function mode
1-0	ICC_DS	R/W	0h	Drive strength control register for ICC pad 0h = 2mA drive setting 1h = 4mA drive setting 2h = 6mA drive setting 3h = 8mA drive setting

7.1.29 IO_CFG_03 Register (Offset = 1Dh) [Reset = 00h]

IO_CFG_03 is shown in Table 7-30.

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This register configures the IO buffers

Table 7-30 IO_CFG_03 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	RESERVED
6	WPD_EN_SDZ	R/W	0h	Week pull down enable - SDZ 0h = pull-dn disabled 1h = pull-dn enabled
5	AD1_PD_EN	R/W	0h	Week pull down enable - AD1 0h = pull-dn disabled 1h = pull-dn enabled
4	AD2_PD_EN	R/W	0h	Week pull down enable - AD2 0h = pull-dn disabled 1h = pull-dn enabled
3	SDOUT_PD_EN	R/W	0h	Weak pull down for SDOUT. 0h = Disabled 1h = Enabled
2	SDIN_PD_EN	R/W	0h	Weak pull down for SDIN. 0h = Disabled 1h = Enabled
1	FSYNC_PD_EN	R/W	0h	Weak pull down for FSYNC. 0h = Disabled 1h = Enabled
0	SBCLK_PD_EN	R/W	0h	Weak pull down for SBCLK. 0h = Disabled 1h = Enabled

7.1.30 NG_CFG0 Register (Offset = 1Eh) [Reset = 60h]

NG_CFG0 is shown in Table 7-31.

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Noise gate hysteresis, threshold level, and enable.

Table 7-31 NG_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	NG_HYST_TIMER	R/W	1h	Noise Gate Entry hysteresis timer 0h = 10ms 1h = 50ms 2h = 100ms 3h = 1000ms
5-3	NG_TH_LVL	R/W	4h	Noise-gate audio threshold level 0h = -85dBFS 1h = -90dBFS 2h = -95dBFS 3h = -100dBFS 4h = -105dBFS 5h = -110dBFS 6h = -115dBFS 7h = -120dBFS
2-0	RESERVED	R	0h	RESERVED

7.1.31 BST_CFG_01 Register (Offset = 21h) [Reset = 12h]

BST_CFG_01 is shown in Table 7-32.

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This register configures internal Boost controller

Table 7-32 BST_CFG_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R	0h	RESERVED
4	BOOST_PHASE_SYNC_EN	R/W	1h	Boost Phase sync enable 0h = Disabled 1h = Enabled
3-2	BOOST_PHASE	R/W	0h	Boost Phase sync delay control, applicable only when BOOST_PHASE_SYNC_EN = 1 0h = Phase shift is 0ns 1h = Phase shift is 65ns 2h = Phase shift is 130ns 3h = Phase shift is 195ns
1	BOOST_PHASE_FROM_ADDRESS_PIN	R/W	1h	Boost Phase shift sync control selected automatically based on i2c slave address detected from Address pin. Applicable only when BOOST_PHASE_SYNC_EN = 1 0h = Disabled 1h = Enabled
0	RESERVED	R	0h	Reserved

7.1.32 BST_CFG_02 Register (Offset = 22h) [Reset = 23h]

BST_CFG_02 is shown in Table 7-33.

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This register configures internal Boost controller

Table 7-33 BST_CFG_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	BST_MODE	R/W	0h	Boost Mode 0h = Class-H 1h = Class-G 2h = Always ON 3h = Always OFF (Passthrough)
5	BOOST_EN	R/W	1h	Boost enable 0h = Disabled (External PVDD mode) 1h = Enabled
4-3	BOOST_MIN_FREQ_SEL	R/W	0h	Boost active mode PFM lower limit 0h = No Limit 1h = 25kHz 2h = 50kHz 3h = RESERVED
2-1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.1.33 INTERRUPT_CFG1 Register (Offset = 25h) [Reset = 00h]

INTERRUPT_CFG1 is shown in Table 7-34.

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This register clears all the latched interrupt registers

Table 7-34 INTERRUPT_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5-2	RESERVED	R	0h	RESERVED
1	INT_CLR_LTCH	R/W	0h	Clear INT_LTCH registers 0h = Don't clear 1h = Clear (self clearing bit)
0	RESERVED	R	0h	RESERVED

7.1.34 TDM_CFG13 Register (Offset = 2Ch) [Reset = 00h]

TDM_CFG13 is shown in Table 7-35.

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This register configures device TDM modes

Table 7-35 TDM_CFG13 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	ECHOREF1_SLEN	R/W	0h	TDM TX Echo Reference Channel 1 time slot length. 0h = Truncate to 8-bits 1h = Left justify to 16-bits
6	ECHOREF1_TX	R/W	0h	TDM TX Echo Reference Channel 1 transmit enable. 0h = Disabled 1h = Enabled
5-0	ECHOREF1_SLOT	R/W	0h	TDM TX Echo Reference Channel 1 time slot.

7.1.35 TDM_CFG15 Register (Offset = 2Eh) [Reset = 00h]

TDM_CFG15 is shown in Table 7-36.

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This register configures device TDM modes

Table 7-36 TDM_CFG15 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Sets the current and voltage data to length of 0h = 16 bits 1h = 12 bits 2h = 8 bits 3h = RESERVED
3-0	RX_CFG	R/W	0h	TDM RX time slot select config. 0h = Channel with time slot equal to I2C address offset 1h = Left channel 2h = Right channel 3h = Stereo downmix (L+R)/2 4h = RESERVED 5h = RESERVED 6h = RESERVED 7h = RESERVED 8h = RESERVED 9h = RESERVED Ah = RESERVED Bh = RESERVED Ch = RESERVED

7.1.36 CLASSD_CFG_01 Register (Offset = 31h) [Reset = 34h]

CLASSD_CFG_01 is shown in Table 7-37.

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D amp configurations - This register configures the class-D amplifier

Table 7-37 CLASSD_CFG_01 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	Reserved
5-4	CLASSD_OUTPUT_EDGERATE_CTRL	R/W	3h	Edgerate programmability control 0h = Class-D output edge rate of approximately 0.5V/ns 1h = Class-D output edge rate of approximately 1V/ns 2h = Reserved Class-D output edge rate of approximately 2V/ns
3	CLASSD_HIZ_MODE	R/W	0h	Amp output state in Noise gate mode 0h = Not Hi-Z 1h = Enabled
2	RESERVED	R	0h	Reserved
1-0	RESERVED	R	0h	RESERVED

7.1.37 CLASSD_CFG_02 Register (Offset = 32h) [Reset = 94h]

CLASSD_CFG_02 is shown in Table 7-38.

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D amp configurations - This register configures the class-D amplifier

Table 7-38 CLASSD_CFG_02 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	EN_Y_BRIDGE_MODE	R/W	1h	Enable/Disable VDD Bridge mode during device operation 0h = VDD Bridge mode disabled 1h = VDD Bridge mode enabled
6	RESERVED	R	0h	Reserved
5-4	RESERVED	R	0h	Reserved
3-2	Y_BRIDGE_HYST_TIMER	R/W	1h	Time hysteresis programmability 0h = 100 us 1h = 500 us 2h = 5ms 3h = 50ms
1-0	RESERVED	R	0h	RESERVED

7.1.38 BST_CFG_05 Register (Offset = 3Bh) [Reset = A7h]

BST_CFG_05 is shown in Table 7-39.

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This register configures internal Boost controller

Table 7-39 BST_CFG_05 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	VBOOST_MAX_CTRL	R/W	A7h	Boost VMAX setting in class-H mode. 54h = 5.54V (Min setting) E5h = 15.11V (Max setting)

7.1.39 THERM_CFG Register (Offset = 3Ch) [Reset = 00h]

THERM_CFG is shown in Table 7-40.

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This register configures thermal warning detection

Table 7-40 THERM_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-1	RESERVED	R	0h	RESERVED
0	EN_THERM_WARN_DET	R/W	0h	Enable control for thermal warning detection feature 0h = Disabled 1h = Enabled

7.1.40 INT_MASK_0 Register (Offset = 5Bh) [Reset = 01h]

INT_MASK_0 is shown in Table 7-41.

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This register configures Masks for Interrupt flags

Table 7-41 INT_MASK_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK0[7]	R/W	0h	Mask for Interrupt due to BOP Inf Hold flag 0h = Don't Mask 1h = Mask
6	INT_MASK0[6]	R/W	0h	Mask for Interrupt due to limiter attenuation flag 0h = Don't Mask 1h = Mask
5	INT_MASK0[5]	R/W	0h	Mask for Interrupt due to supply less than inf pt flag 0h = Don't Mask 1h = Mask
4	INT_MASK0[4]	R/W	0h	Mask for Interrupt due to limiter active flag 0h = Don't Mask 1h = Mask
3	INT_MASK0[3]	R/W	0h	Mask for Interrupt due to brownout detected flag 0h = Don't Mask 1h = Mask
2	INT_MASK0[2]	R/W	0h	Mask for Interrupt due to bop active flag 0h = Don't Mask 1h = Mask
1	INT_MASK0[1]	R/W	0h	Mask for Interrupt due to device active flag 0h = Don't Mask 1h = Mask
0	RESERVED	R	0h	Reserved

7.1.41 INT_MASK_1 Register (Offset = 5Ch) [Reset = 1Fh]

INT_MASK_1 is shown in Table 7-42.

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This register configures Masks for Interrupt flags

Table 7-42 INT_MASK_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK1[7]	R/W	0h	Mask for Interrupt due to PVDD Under voltage 0h = Don't Mask 1h = Mask
6	INT_MASK1[6]	R/W	0h	Mask for Interrupt due to VBAT 2S supply under voltage 0h = Don't Mask 1h = Mask
5	INT_MASK1[5]	R/W	0h	Mask for Interrupt due to DacMod overflow 0h = Don't Mask 1h = Mask
4	INT_MASK1[4]	R/W	1h	Mask for Interrupt due to Thermal Warning 135C 0h = Don't Mask 1h = Mask
3	INT_MASK1[3]	R/W	1h	Mask for Interrupt due to Thermal Warning 125C 0h = Don't Mask 1h = Mask
2	INT_MASK1[2]	R/W	1h	Mask for Interrupt due to Thermal Warning 115C 0h = Don't Mask 1h = Mask
1	INT_MASK1[1]	R/W	1h	Mask for Interrupt due to Thermal Warning 105C 0h = Don't Mask 1h = Mask
0	INT_MASK1[0]	R/W	1h	Mask for Interrupt due to DSP Mask for Interrupt output 0h = Don't Mask 1h = Mask

7.1.42 INT_MASK_2 Register (Offset = 5Dh) [Reset = 00h]

INT_MASK_2 is shown in Table 7-43.

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This register configures Masks for Interrupt flags

Table 7-43 INT_MASK_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK2[7]	R/W	0h	Mask for Interrupt due to watchdog expiry 0h = Don't Mask 1h = Mask
6	RESERVED	R	0h	Reserved
5	INT_MASK2[5]	R/W	0h	Mask for Interrupt due to frame out of sync 0h = Don't Mask 1h = Mask
4	INT_MASK2[4]	R/W	0h	Mask for Interrupt due to PLL clock error 0h = Don't Mask 1h = Mask
3	INT_MASK2[3]	R/W	0h	Mask for Interrupt due to tdm error 0h = Don't Mask 1h = Mask
2	INT_MASK2[2]	R/W	0h	Mask for Interrupt due to ratio change error flag 0h = Don't Mask 1h = Mask
1	INT_MASK2[1]	R/W	0h	Mask for Interrupt due to fs change error flag 0h = Don't Mask 1h = Mask
0	INT_MASK2[0]	R/W	0h	Mask for Interrupt due to invalid ratio fs flag 0h = Don't Mask 1h = Mask

7.1.43 INT_MASK_3 Register (Offset = 5Fh) [Reset = 1Ah]

INT_MASK_3 is shown in Table 7-44.

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This register configures Masks for Interrupt flags

Table 7-44 INT_MASK_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK4[7]	R/W	0h	Mask for Interrupt due to vbat_por 0h = Don't Mask 1h = Mask
7	INT_MASK3[7]	R/W	0h	Mask for Interrupt due to over temperature detected 0h = Don't Mask 1h = Mask
6	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	INT_MASK3[3]	R/W	1h	Mask for Interrupt due to Class-D Over current protection 0h = Don't Mask 1h = Mask
3	RESERVED	R	0h	Reserved
2	INT_MASK4[2]	R/W	0h	Mask for Interrupt due to clock halt flag. This interrupt also flags errors due to Pre-power-up clock error while using Wake-up-on-ASI feature 0h = Don't Mask 1h = Mask
2	INT_MASK3[2]	R/W	0h	Mask for Interrupt due to pvdd_ov_flag 0h = Don't Mask 1h = Mask
1	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.1.44 INT_LATCH_0 Register (Offset = 60h) [Reset = 00h]

INT_LATCH_0 is shown in Table 7-45.

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This register provides the status of latched interrupts

Table 7-45 INT_LATCH_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH0[7]	R	0h	Interrupt due to BOP Inf Hold flag 0h = No interrupt 1h = Interrupt
6	INT_LTCH0[6]	R	0h	Interrupt due to limiter attenuation flag 0h = No interrupt 1h = Interrupt
5	INT_LTCH0[5]	R	0h	Interrupt due to supply less than inf pt flag 0h = No interrupt 1h = Interrupt
4	INT_LTCH0[4]	R	0h	Interrupt due to limiter active flag 0h = No interrupt 1h = Interrupt
3	INT_LTCH0[3]	R	0h	Interrupt due to brownout detected flag 0h = No interrupt 1h = Interrupt
2	INT_LTCH0[2]	R	0h	Interrupt due to bop active flag 0h = No interrupt 1h = Interrupt
1	INT_LTCH0[1]	R	0h	Live Interrupt due to device active flag 0h = No interrupt 1h = Interrupt
0	RESERVED	R	0h	Reserved

7.1.45 INT_LATCH_1 Register (Offset = 61h) [Reset = 00h]

INT_LATCH_1 is shown in Table 7-46.

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This register provides the status of latched interrupts

Table 7-46 INT_LATCH_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH1[7]	R	0h	Interrupt due to PVDD under voltage detection 0h = No interrupt 1h = Interrupt
6	INT_LTCH1[6]	R	0h	Interrupt due to VBAT2S under voltage detection 0h = No interrupt 1h = Interrupt
5	INT_LTCH1[5]	R	0h	Interrupt due to DacMod overflow 0h = No interrupt 1h = Interrupt
4	INT_LTCH1[4]	R	0h	Interrupt due to Thermal Warning 135C 0h = No interrupt 1h = Interrupt
3	INT_LTCH1[3]	R	0h	Interrupt due to Thermal Warning 125C 0h = No interrupt 1h = Interrupt
2	INT_LTCH1[2]	R	0h	Interrupt due to Thermal Warning 115C 0h = No interrupt 1h = Interrupt
1	INT_LTCH1[1]	R	0h	Interrupt due to Thermal Warning 105C 0h = No interrupt 1h = Interrupt
0	INT_LTCH1[0]	R	0h	Interrupt due to DSP Mask for Interrupt output 0h = No interrupt 1h = Interrupt

7.1.46 INT_LATCH_2 Register (Offset = 62h) [Reset = 00h]

INT_LATCH_2 is shown in Table 7-47.

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This register provides the status of latched interrupts

Table 7-47 INT_LATCH_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH2[7]	R	0h	Interrupt due to watchdog expiry 0h = No interrupt 1h = Interrupt
6	RESERVED	R	0h	Reserved
5	INT_LTCH2[5]	R	0h	Interrupt due to frame out of sync 0h = No interrupt 1h = Interrupt
4	INT_LTCH2[4]	R	0h	Interrupt due to PLL clock error 0h = No interrupt 1h = Interrupt
3	INT_LTCH2[3]	R	0h	Interrupt due to tdm error 0h = No interrupt 1h = Interrupt
2	INT_LTCH2[2]	R	0h	Interrupt due to ratio change error flag 0h = No interrupt 1h = Interrupt
1	INT_LTCH2[1]	R	0h	Interrupt due to fs change error flag 0h = No interrupt 1h = Interrupt
0	INT_LTCH2[0]	R	0h	Interrupt due to invalid ratio fs flag 0h = No interrupt 1h = Interrupt

7.1.47 INT_LATCH_3 Register (Offset = 63h) [Reset = 00h]

INT_LATCH_3 is shown in Table 7-48.

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This register provides the status of latched interrupts

Table 7-48 INT_LATCH_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH3[7]	R	0h	Interrupt due to over temperature detected 0h = No interrupt 1h = Interrupt
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	INT_LTCH3[3]	R	0h	Interrupt due to Class-D Over current protection 0h = No interrupt 1h = Interrupt
2	INT_LTCH3[2]	R	0h	Interrupt due to Over voltage on PVDD supply. 0h = No interrupt 1h = Interrupt
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.1.48 INT_LATCH_4 Register (Offset = 64h) [Reset = 00h]

INT_LATCH_4 is shown in Table 7-49.

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This register provides the status of latched interrupts

Table 7-49 INT_LATCH_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH4[7]	R	0h	Interrupt due to VBAT under voltage detection 0h = No interrupt 1h = Interrupt
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	INT_LTCH4[2]	R	0h	Interrupt due to clock halt flag 0h = No interrupt 1h = Interrupt
1	RESERVED	R	0h	Reserved
0	RESERVED	R	0h	Reserved

7.1.49 NG_IDLE_STATUS Register (Offset = 65h) [Reset = 00h]

NG_IDLE_STATUS is shown in Table 7-50.

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This register provides the status of latched interrupts

Table 7-50 NG_IDLE_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	NG_STATUS	R	0h	Noise mode status bit 0h = Device not in Noise gate mode 1h = Device in Noise gate mode
6	MUSIC_EFF_STATUS	R	0h	Music efficiency mode status bit 0h = Device not in music efficiency mode 1h = Device in music efficiency mode
5-0	RESERVED	R	0h	RESERVED

7.1.50 INT_MASK_5 Register (Offset = 66h) [Reset = 00h]

INT_MASK_5 is shown in Table 7-51.

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This register configures Masks for Interrupt flags

Table 7-51 INT_MASK_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_MASK5[7]	R/W	0h	Mask for Interrupt due to completion of factory calibration 0h = Don't Mask 1h = Mask
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	INT_MASK5[4]	R/W	0h	Mask for Interrupt due to detection of short circuit 0h = Don't Mask 1h = Mask
3	INT_MASK5[3]	R/W	0h	Mask for Interrupt due to detection of open circuit 0h = Don't Mask 1h = Mask
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h
0	RESERVED	R	0h

7.1.51 INT_LATCH_5 Register (Offset = 67h) [Reset = 00h]

INT_LATCH_5 is shown in Table 7-52.

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This register provides the status of latched interrupts of fct

Table 7-52 INT_LATCH_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	INT_LTCH5[7]	R	0h	Interrupt due to completion of factory calibration 0h = No interrupt 1h = Interrupt
6	RESERVED	R	0h	Reserved
5	RESERVED	R	0h	Reserved
4	INT_LTCH5[4]	R	0h	Interrupt due to detection of short circuit 0h = No interrupt 1h = Interrupt
3	INT_LTCH5[3]	R	0h	Interrupt due to detection of open circuit 0h = No interrupt 1h = Interrupt
2	INT_LTCH5[2]	R	0h	Interrupt due to detection of silence in input audio 0h = No interrupt 1h = Interrupt
1	RESERVED	R	0h
0	RESERVED	R	0h

7.1.52 REV_ID Register (Offset = 78h) [Reset = 00h]

REV_ID is shown in Table 7-53.

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Returns REV and PG ID.

Table 7-53 REV_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	REV_ID	R	0h	Returns the revision ID.

7.1.53 BOOK Register (Offset = 7Fh) [Reset = 00h]

BOOK is shown in Table 7-54.

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Device's memory map is divided into pages and books. This register sets the book.

Table 7-54 BOOK Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	BOOK	R/W	0h	Sets the device book.

7.1 PAGE_0 Registers

7.1.1 Page Register (Offset = 0h) [Reset = 00h]

7.1.2 SW_RESET Register (Offset = 1h) [Reset = 00h]

7.1.3 PWR_CTL Register (Offset = 2h) [Reset = 02h]

7.1.4 DEVICE_CFG_01 Register (Offset = 3h) [Reset = C0h]

7.1.5 DEVICE_CFG_02 Register (Offset = 4h) [Reset = 8Ch]

7.1.6 DEVICE_CFG_03 Register (Offset = 5h) [Reset = 00h]

7.1.7 DEVICE_CFG_04 Register (Offset = 6h) [Reset = 04h]

7.1.8 DEVICE_CFG_05 Register (Offset = 7h) [Reset = 00h]

7.1.9 TDM_CFG1 Register (Offset = 8h) [Reset = 82h]

7.1.10 TDM_CFG2 Register (Offset = 9h) [Reset = 0Ah]

7.1.11 TDM_CFG3 Register (Offset = Ah) [Reset = 10h]

7.1.12 TDM_CFG5 Register (Offset = Ch) [Reset = 13h]

7.1.13 TDM_CFG6 Register (Offset = Dh) [Reset = 02h]

7.1.14 TDM_CFG7 Register (Offset = Eh) [Reset = 00h]

7.1.15 TDM_CFG8 Register (Offset = Fh) [Reset = 04h]

7.1.16 TDM_CFG9 Register (Offset = 10h) [Reset = 05h]

7.1.17 TDM_CFG10 Register (Offset = 11h) [Reset = 07h]

7.1.18 TDM_CFG11 Register (Offset = 12h) [Reset = 06h]

7.1.19 TDM_CFG12 Register (Offset = 13h) [Reset = 12h]

7.1.20 TDM_DET Register (Offset = 14h) [Reset = 7Fh]

7.1.21 MONITOR_CFG_01 Register (Offset = 15h) [Reset = 00h]

7.1.22 MONITOR_CFG_02 Register (Offset = 16h) [Reset = 30h]

7.1.23 LIM_CFG_0 Register (Offset = 17h) [Reset = 00h]

7.1.24 BOP_CFG_0 Register (Offset = 18h) [Reset = 00h]

7.1.25 TONE_GEN_01 Register (Offset = 19h) [Reset = 40h]

7.1.26 TONE_GEN_02 Register (Offset = 1Ah) [Reset = 96h]

7.1.27 IO_CFG_01 Register (Offset = 1Bh) [Reset = 01h]

7.1.28 IO_CFG_02 Register (Offset = 1Ch) [Reset = 3Ch]

7.1.29 IO_CFG_03 Register (Offset = 1Dh) [Reset = 00h]

7.1.30 NG_CFG0 Register (Offset = 1Eh) [Reset = 60h]

7.1.31 BST_CFG_01 Register (Offset = 21h) [Reset = 12h]

7.1.32 BST_CFG_02 Register (Offset = 22h) [Reset = 23h]

7.1.33 INTERRUPT_CFG1 Register (Offset = 25h) [Reset = 00h]

7.1.34 TDM_CFG13 Register (Offset = 2Ch) [Reset = 00h]

7.1.35 TDM_CFG15 Register (Offset = 2Eh) [Reset = 00h]

7.1.36 CLASSD_CFG_01 Register (Offset = 31h) [Reset = 34h]

7.1.37 CLASSD_CFG_02 Register (Offset = 32h) [Reset = 94h]

7.1.38 BST_CFG_05 Register (Offset = 3Bh) [Reset = A7h]

7.1.39 THERM_CFG Register (Offset = 3Ch) [Reset = 00h]

7.1.40 INT_MASK_0 Register (Offset = 5Bh) [Reset = 01h]

7.1.41 INT_MASK_1 Register (Offset = 5Ch) [Reset = 1Fh]

7.1.42 INT_MASK_2 Register (Offset = 5Dh) [Reset = 00h]

7.1.43 INT_MASK_3 Register (Offset = 5Fh) [Reset = 1Ah]

7.1.44 INT_LATCH_0 Register (Offset = 60h) [Reset = 00h]

7.1.45 INT_LATCH_1 Register (Offset = 61h) [Reset = 00h]

7.1.46 INT_LATCH_2 Register (Offset = 62h) [Reset = 00h]

7.1.47 INT_LATCH_3 Register (Offset = 63h) [Reset = 00h]

7.1.48 INT_LATCH_4 Register (Offset = 64h) [Reset = 00h]

7.1.49 NG_IDLE_STATUS Register (Offset = 65h) [Reset = 00h]

7.1.50 INT_MASK_5 Register (Offset = 66h) [Reset = 00h]

7.1.51 INT_LATCH_5 Register (Offset = 67h) [Reset = 00h]

7.1.52 REV_ID Register (Offset = 78h) [Reset = 00h]

7.1.53 BOOK Register (Offset = 7Fh) [Reset = 00h]