SLASFM6
October 2026
TAS2573
ADVANCE INFORMATION
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Timing Diagrams
5.8
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Device Functional Modes
6.3.1
Operational Modes
6.3.1.1
Hardware Shutdown
6.3.1.2
Software Power Modes Control and Software Reset
6.3.1.3
Efficiency and power saving modes
6.3.1.3.1
Noise Gate
6.3.1.3.2
Music Efficiency Mode
6.3.1.3.3
VDD Y-bridge
6.3.1.3.4
Class-H Boost
6.3.1.4
2S Battery Mode
6.3.1.5
Low voltage battery mode
6.3.1.6
External PVDD Mode
6.3.2
Faults and Status
6.3.2.1
Interrupt generation and clearing
6.4
Feature Description
6.4.1
PurePath™ Console 3 Software
6.4.2
Playback Signal Path
6.4.2.1
Digital Signal Processor
6.4.2.1.1
Algorithm Blocks
6.4.2.1.2
Algorithm Features
6.4.2.1.3
Factory Calibration
6.4.2.2
Digital Volume Control and Amplifier Output Level
6.4.2.3
High Pass Filter
6.4.2.4
Class-D Amplifier
6.4.2.5
Supply Tracking Limiters with Brown Out Prevention
6.4.2.5.1
Voltage Limiter and Clipping protection
6.4.2.6
Tone Generator
6.4.3
Digital Audio Serial Interface
6.4.4
Boost
6.4.5
Speaker current and voltage (IV) sensing
6.4.6
Supply Voltage Monitors
6.4.7
Thermal Protection
6.4.8
Clocks and PLL
6.4.8.1
Auto clock based wakeup and clock errors
6.4.9
Digital IO pins
6.5
Programming
6.5.1
I2C Control Interface
6.5.2
I2C Address Selection
6.5.3
General I2C Operation
6.5.4
I2C Single-Byte and Multiple-Byte Transfers
6.5.5
I2C Single-Byte Write
6.5.6
I2C Multiple-Byte Write
6.5.7
I2C Single-Byte Read
6.5.8
I2C Multiple-Byte Read
7
Register Maps
7.1
PAGE_0 Registers
7.2
PAGE_1 Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Mono/Stereo Configuration
8.2.2.2
Boost Converter Passive Devices
8.2.2.3
EMI Passive Devices
8.2.2.4
Miscellaneous Passive Devices
8.2.3
Application Performance Plots
8.2.4
What to Do and What Not to Do
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Revision History
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
11.1
Package Option Addendum
11.2
Tape and Reel Information
1
Features
Powerful class-D amplifier
8.5W 1% THD+N (8Ω at 4.4V)
8.8W 1% THD+N (4Ω at 4.4V)
15V boost with 5.1A max current limit
Best in class efficiency
Upto 89% efficiency at system level for 8Ω load
19mW idle channel power in active mode
5.5mW idle channel power in Noise gate mode
Integrated 1.8V Y-bridge and 33mV step class-H
High performance audio channel
4.2µV A-wt. idle channel noise
114dB Dynamic Range
-90dB THDN
Low EMI performance with ERC and SSM
< 1µs chip to chip group delay matching
Advanced integrated features
Speaker Protection and Advanced Battery Guard with integrated IV sense
Audio tuning with EQ, DRC, DEQ
Speaker Rattle Noise Suppression algorithm
Signal detection high efficiency modes
High accuracy voltage monitor & temp sensor
Ease of use features
1cell, 2cell and 3cell Li-ion battery support
Clock based power up/down
Auto clock rate detection: 16kHz to 192kHz
External 14V PVDD supply support
MCLK free operation
Thermal and over current protection
Programmable drive strength IO buffers
Power Supplies and user interface
VBAT:
2.0
V to 5.5V
VDD: 1.65V to 1.95V
IOVDD: 1.2V or 1.8V
VBAT_SNS: 2.0V to 10.0V
PVDD: 2.5V to 14V (Ext. PVDD mode)
I
2
S/TDM: 8 channels
I
2
C: 4 selectable addresses
48-Ball, 0.35mm Pitch, WCSP package