SLASFM6 October   2026 TAS2573

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Software Power Modes Control and Software Reset
        3. 6.3.1.3 Efficiency and power saving modes
          1. 6.3.1.3.1 Noise Gate
          2. 6.3.1.3.2 Music Efficiency Mode
          3. 6.3.1.3.3 VDD Y-bridge
          4. 6.3.1.3.4 Class-H Boost
        4. 6.3.1.4 2S Battery Mode
        5. 6.3.1.5 Low voltage battery mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Signal Processor
          1. 6.4.2.1.1 Algorithm Blocks
          2. 6.4.2.1.2 Algorithm Features
          3. 6.4.2.1.3 Factory Calibration
        2. 6.4.2.2 Digital Volume Control and Amplifier Output Level
        3. 6.4.2.3 High Pass Filter
        4. 6.4.2.4 Class-D Amplifier
        5. 6.4.2.5 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.5.1 Voltage Limiter and Clipping protection
        6. 6.4.2.6 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
      4. 6.4.4 Boost
      5. 6.4.5 Speaker current and voltage (IV) sensing
      6. 6.4.6 Supply Voltage Monitors
      7. 6.4.7 Thermal Protection
      8. 6.4.8 Clocks and PLL
        1. 6.4.8.1 Auto clock based wakeup and clock errors
      9. 6.4.9 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE_0 Registers
    2. 7.2 PAGE_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

8.2 Typical Application

Diagrams below shows the typical application connections for 1S, low voltage 1S battery and 2S Li-Ion battery and for the external PVDD or 3S Battery connection. VBAT_SNS pin connection is optional for 1S mode and if not used, VBAT_SNS pin must be grounded. AD1 and AD2 are used for address detection and can be tied to IOVDD or ground to support up to four I2C target addresses as described in I2C Mode Address selection section (Section 6.5.2 ).

System can use same 1.8V supply source to power the IOVDD and VDD if required. The decoupling caps C2 and C3 must still be placed close to the device pins.

VDD signal to supply is critical for device performance and wide trace must be used from the source PMIC to the VDD pin to minimize the parasitic inductance. VDD supply ripple must be kept at minimum and the trace must be connected to common supply plane.

TAS2573 Application Diagram for 1S system Figure 8-1 Application Diagram for 1S system
TAS2573 Application Diagram for low voltage 1S Battery system Figure 8-2 Application Diagram for low voltage 1S Battery system
TAS2573 Application Diagram for 2S Battery system Figure 8-3 Application Diagram for 2S Battery system
TAS2573 Application Diagram for External PVDD or 3S Battery system Figure 8-4 Application Diagram for External PVDD or 3S Battery system
Table 8-1 Recommended External Components
ComponentDescriptionSpecificationMinTypMaxUnit
L1Boost Convertor InductorInductance, 20% Tolerance0.471µH
Saturation current5.3A
L2, L3Optional EMI Filter Inductors (must use R1, R2 if L2, L3 are used)DC Current2A
C1, C2DREG, IOVDD decapsCapacitance, 20% tolerance1µF
Voltage rating26.3V
C3VDD decapCapacitance, 20% tolerance2.2µF
Voltage rating26.3V
C4VBAT decapCapacitance, 20% tolerance1µF
Voltage rating6.310V
C5VBAT Power decapCapacitance, 20% tolerance10µF
Voltage rating6.310V
C5aVBAT 2S Power decapCapacitance, 20% tolerance10µF
Voltage rating1016V
C6PVDD Low ESL decapCapacitance, 20% tolerance0.1µF
Voltage rating1625V
C7, C8, C12(1)PVDD Power decapCapacitance, 20% tolerance10µF
Voltage rating1625V
Effective total PVDD Capacitance at 13V DC after deratings for 1S battery system3µF
Effective total PVDD Capacitance at 13V DC after deratings for 2S battery system

Note: C12 is not required for 2S system to meet the derating spec.

2µF
C9GREG decapCapacitance, 20% tolerance0.1µF
Voltage rating6.310V
C10, C11Optional EMI Filter capacitors (must use L2, L3 if C10, C11 are used) Voltage rating2xPVDDV
R1, R2Optional Voltage sense resistors ( Must be used if L2, L3 are used)Resistance, 5% tolerance12.24.7kΩ
Temp Coefficient300ppm/C
Power 0.01W
(1) Number of capacitors can be reduced by replacing the 10µF with higher value capacitors which meet the cap derating requirement. For example Two GRM188C61E206ME01 cap meets the spec for 1S battery system and save the board space by reducing one 0603 package size capacitor.