SLLSFT1 Data sheet

SLLSFT1 October 2026 TIOM2212

ADVANCE INFORMATION

7.3.12.1 device Registers

Table 7-3 lists the memory-mapped registers for the device registers. All register offset addresses not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.

Table 7-3 DEVICE Registers

Offset	Acronym	Register Name	Section
0h	Revision Identifier	Device revision identifier	Section 3.12.1.1
1h	Clock Configuration	System clock configuration	Section 3.12.1.2
2h	Device Logic Interrupt Mask		Section 3.12.1.3
3h	Device Phy Interrupt Mask		Section 3.12.1.4
4h	Device Control		Section 3.12.1.5
5h	Synchronization	Device channels soft master trigger synchronizer	Section 3.12.1.6
6h	DEV6		Section 3.12.1.7
7h	DEV7		Section 3.12.1.8
8h	DEV8		Section 3.12.1.9
9h	DEV9		Section 3.12.1.10
Ah	DEV10		Section 3.12.1.11
Bh	DEV11		Section 3.12.1.12
Ch	DEV12		Section 3.12.1.13
Dh	DEV13		Section 3.12.1.14
Eh	DEV14		Section 3.12.1.15
Fh	DEV15		Section 3.12.1.16
10h	DEV16		Section 3.12.1.17
11h	DEV17		Section 3.12.1.18
12h	DEV18		Section 3.12.1.19
13h	DEV19		Section 3.12.1.20
14h	DEV20		Section 3.12.1.21
15h	DEV21		Section 3.12.1.22
16h	Device Logic Status		Section 3.12.1.23
17h	Device Phy Status		Section 3.12.1.24
18h	Device Logic Interrupt Request		Section 3.12.1.25
19h	Device Phy Interrupt Request		Section 3.12.1.26
1Ah	DEV26		Section 3.12.1.27
1Bh	Extended Feature Support 0		Section 3.12.1.28
1Ch	Extended Feature Support 1		Section 3.12.1.29
1Dh	CQ Driver Max Auto Recovery		Section 3.12.1.30
1Eh	LP Max Auto Recovery		Section 3.12.1.31
1Fh	HSS Max Auto Recovery		Section 3.12.1.32

Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.

Table 7-4 device Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	R C	Read to Clear
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

3.12.1.1 Revision Identifier Register (Offset = 0h) [Reset = 00h]

Revision Identifier is shown in Table 7-5.

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Table 7-5 Revision Identifier Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	MAJOR	R	0h	Major device revision identifier Identifies full-layer die revision 0h = revision 0 (original release) 1h = revision 1 2h = revision 2 3h = revision 3 4h = revision 4 5h = revision 5 6h = revision 6 7h = revision 7 8h = revision 8 9h = revision 9 Ah = revision 10 Bh = revision 11 Ch = revision 12 Dh = revision 13 Eh = revision 14 Fh = revision 15
3-0	MINOR	R	0h	Minor device revision identifier Identifies metal-layer die revision 0h = revision 0 (original release) 1h = revision 1 2h = revision 2 3h = revision 3 4h = revision 4 5h = revision 5 6h = revision 6 7h = revision 7 8h = revision 8 9h = revision 9 Ah = revision 10 Bh = revision 11 Ch = revision 12 Dh = revision 13 Eh = revision 14 Fh = revision 15

3.12.1.2 Clock Configuration Register (Offset = 1h) [Reset = 00h]

Clock Configuration is shown in Table 7-6.

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Table 7-6 Clock Configuration Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	Reserved
5-4	ESR	R/W	0h	Effective series resistance select Sets the effective series resistance used in current sensing for the L+ supply driver; see [section X.Y] for more information 0h = 200 andx3A9;# 1h = 100 andx3A9;# 2h = 75 andx3A9;# 3h = 50 andx3A9;#
3	CLKO_EN	R/W	0h	Clock output enable Enables output of internal oscillator on CLKO pin 0h = CLKO pin is high impedance 1h = internal crystal oscillator clock output on CLKO pin
2	CLKIN_EN	R/W	0h	Clock input enable Enables dependence of external clock on CLKIN pin 0h = CLKIN input is ignored 1h = external clock input on CLKIN pin expected
1	RESERVED	R	0h	Reserved
0	XTAL_EN	R/W	0h	Crystal oscillator enable Enables internal oscillator 0h = crystal oscillator disabled 1h = crystal oscillator enabled

3.12.1.3 Device Logic Interrupt Mask Register (Offset = 2h) [Reset = 00h]

Device Logic Interrupt Mask is shown in Table 7-7.

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Table 7-7 Device Logic Interrupt Mask Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	MASK	R/W	0h	Device logic interrupt mask Sets mask to ignore interrupt events; see [section] for more details 0h = interrupt not masked 1h = interrupt masked

3.12.1.4 Device Phy Interrupt Mask Register (Offset = 3h) [Reset = 00h]

Device Phy Interrupt Mask is shown in Table 7-8.

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Table 7-8 Device Phy Interrupt Mask Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	MASK	R/W	0h	Device physical interrupt mask Sets mask to ignore interrupt events; see [section] for more details 0h = interrupt not masked 1h = interrupt masked

3.12.1.5 Device Control Register (Offset = 4h) [Reset = 00h]

Device Control is shown in Table 7-9.

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Table 7-9 Device Control Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1	EN	R/W	0h	Device enable Enables device 0h = device disabled 1h = device enabled
0	RST	W	0h	Device digital soft reset Resets device 0h = normal operation 1h = digital reset

3.12.1.6 Synchronization Register (Offset = 5h) [Reset = 00h]

Synchronization is shown in Table 7-10.

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Table 7-10 Synchronization Register Field Descriptions

Bit	Field	Type	Reset	Description
7-5	RESERVED	R	0h	Reserved
4	LED_SYNC	W	0h	Sync all LED Synchronize all LED's 0h = LEDs not synchronized 1h = LEDs synchronized
3-2	RESERVED	R	0h	Reserved
1	SYNCB	W	0h	Channel B sync control Triggers the immediate transfer of data in the TX buffer 0h = no transmission 1h = transmit data
0	SYNCA	W	0h	Channel A sync control Triggers the immediate transfer of data in the TX buffer 0h = no transmission 1h = transmit data

3.12.1.7 DEV6 Register (Offset = 6h) [Reset = 00h]

DEV6 is shown in Table 7-11.

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Table 7-11 DEV6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.8 DEV7 Register (Offset = 7h) [Reset = 00h]

DEV7 is shown in Table 7-12.

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Table 7-12 DEV7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.9 DEV8 Register (Offset = 8h) [Reset = 00h]

DEV8 is shown in Table 7-13.

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Table 7-13 DEV8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.10 DEV9 Register (Offset = 9h) [Reset = 00h]

DEV9 is shown in Table 7-14.

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Table 7-14 DEV9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.11 DEV10 Register (Offset = Ah) [Reset = 00h]

DEV10 is shown in Table 7-15.

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Table 7-15 DEV10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.12 DEV11 Register (Offset = Bh) [Reset = 00h]

DEV11 is shown in Table 7-16.

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Table 7-16 DEV11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.13 DEV12 Register (Offset = Ch) [Reset = 00h]

DEV12 is shown in Table 7-17.

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Table 7-17 DEV12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.14 DEV13 Register (Offset = Dh) [Reset = 00h]

DEV13 is shown in Table 7-18.

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Table 7-18 DEV13 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.15 DEV14 Register (Offset = Eh) [Reset = 00h]

DEV14 is shown in Table 7-19.

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Table 7-19 DEV14 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.16 DEV15 Register (Offset = Fh) [Reset = 00h]

DEV15 is shown in Table 7-20.

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Table 7-20 DEV15 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.17 DEV16 Register (Offset = 10h) [Reset = 00h]

DEV16 is shown in Table 7-21.

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Table 7-21 DEV16 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.18 DEV17 Register (Offset = 11h) [Reset = 00h]

DEV17 is shown in Table 7-22.

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Table 7-22 DEV17 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.19 DEV18 Register (Offset = 12h) [Reset = 00h]

DEV18 is shown in Table 7-23.

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Table 7-23 DEV18 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.20 DEV19 Register (Offset = 13h) [Reset = 00h]

DEV19 is shown in Table 7-24.

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Table 7-24 DEV19 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.21 DEV20 Register (Offset = 14h) [Reset = 00h]

DEV20 is shown in Table 7-25.

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Table 7-25 DEV20 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.22 DEV21 Register (Offset = 15h) [Reset = 00h]

DEV21 is shown in Table 7-26.

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Table 7-26 DEV21 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.23 Device Logic Status Register (Offset = 16h) [Reset = 00h]

Device Logic Status is shown in Table 7-27.

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Table 7-27 Device Logic Status Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CQB_AR	R	0h	C/Q channel B overcurrent recovery retry limit reached Indicates driver has reached maximum number of retries from field CQB_DRV_MAX_AR 0h = limit not reached 1h = limit reached
6	CQA_AR	R	0h	C/Q channel A overcurrent recovery retry limit reached Indicates driver has reached maximum number of retries from field CQA_DRV_MAX_AR 0h = limit not reached 1h = limit reached
5	LPB_AR	R	0h	L+ channel B overcurrent recovery retry limit reached Indicates driver has reached maximum number of retries from field LPB_MAX_AR 0h = limit not reached 1h = limit reached
4	LPA_AR	R	0h	L+ channel A overcurrent recovery retry limit reached Indicates driver has reached maximum number of retries from field LPA_MAX_AR 0h = limit not reached 1h = limit reached
3	HSSB_AR	R	0h	High side switch (HSS) channel B overcurrent/reverse polarity recovery retry limit reached Indicates driver has reached maximum number of retries from field HSSB_MAX_AR 0h = limit not reached 1h = limit reached
2	HSSA_AR	R	0h	High side switch (HSS) channel A overcurrent/reverse polarity recovery retry limit reached Indicates driver has reached maximum number of retries from field HSSA_MAX_AR 0h = limit not reached 1h = limit reached
1	XTAL_OR_EXT_GOOD	R	0h	Internal crystal or external clock good Indicates internal crystal or external clock has achieved initialization 0h = initialization not complete 1h = initialization complete
0	INIT_DONE	R	0h	Device initialization complete Indicates device has completed startup and is ready to begin communication 0h = initialization not complete 1h = initialization complete

3.12.1.24 Device Phy Status Register (Offset = 17h) [Reset = 00h]

Device Phy Status is shown in Table 7-28.

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Table 7-28 Device Phy Status Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RESERVED	R	0h	Reserved
5	LPB_WARN	R	0h	LPB Warning LPB Warning 0h = no LPB warning 1h = LPB warning
4	LPA_WARN	R	0h	LPA Warning LPA Warning 0h = no LPA warning 1h = LPA warning
3	RESERVED	R	0h	Reserved
2	VCC_OV	R	0h	VCC over voltage status Indicates voltage on VCC pin has exceeded overvoltage limit [more details on OV limit] 0h = limit not reached 1h = limit reached
1	VCC_WARN	R	0h	VCC under voltage warning Indicates voltage on VCC pin has decreased below undervoltage warning limit [more details on UV limit] 0h = limit not reached 1h = limit reached
0	VCC_UVLO	R	0h	VCC UVLO status Indicates voltage on VCC pin has decreased below UVLO limit [more details on UV limit] 0h = limit not reached 1h = limit reached

3.12.1.25 Device Logic Interrupt Request Register (Offset = 18h) [Reset = 00h]

Device Logic Interrupt Request is shown in Table 7-29.

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Table 7-29 Device Logic Interrupt Request Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CQB_AR	RC	0h	C/Q channel B overcurrent recovery retry limit reached Indicates driver has reached maximum number of retries from field CQB_DRV_MAX_AR 0h = limit not reached 1h = limit reached
6	CQA_AR	RC	0h	C/Q channel A overcurrent recovery retry limit reached Indicates driver has reached maximum number of retries from field CQA_DRV_MAX_AR 0h = limit not reached 1h = limit reached
5	LPB_AR	RC	0h	L+ channel B overcurrent recovery retry limit reached Indicates driver has reached maximum number of retries from field LPB_MAX_AR 0h = limit not reached 1h = limit reached
4	LPA_AR	RC	0h	L+ channel A overcurrent recovery retry limit reached Indicates driver has reached maximum number of retries from field LPA_MAX_AR 0h = limit not reached 1h = limit reached
3	HSSB_AR	RC	0h	High side switch (HSS) channel B overcurrent/reverse polarity recovery retry limit reached Indicates driver has reached maximum number of retries from field HSSB_MAX_AR 0h = limit not reached 1h = limit reached
2	HSSA_AR	RC	0h	High side switch (HSS) channel A overcurrent/reverse polarity recovery retry limit reached Indicates driver has reached maximum number of retries from field HSSA_MAX_AR 0h = limit not reached 1h = limit reached
1	XTAL_OR_EXT_GOOD_CHANGE	RC	0h	Change in Internal crystal or external clock good Indicates internal crystal or external clock has changed 0h = no change in clock 1h = change in clock
0	INIT_DONE	RC	0h	Device initialization complete Indicates device has completed startup and is ready to begin communication 0h = initialization not complete 1h = initialization complete

3.12.1.26 Device Phy Interrupt Request Register (Offset = 19h) [Reset = 00h]

Device Phy Interrupt Request is shown in Table 7-30.

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Table 7-30 Device Phy Interrupt Request Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	RC	0h	Reserved
6	RESERVED	RC	0h	Reserved
5	LPB_WARN	RC	0h	LPB Warning LPB Warning 0h = no LPB warning 1h = LPB warning
4	LPA_WARN	RC	0h	LPA Warning LPA Warning 0h = no LPA warning 1h = LPA warning
3	RESERVED	RC	0h	Reserved
2	VCC_OV	RC	0h	VCC over voltage status Indicates voltage on VCC pin has exceeded overvoltage limit [more details on OV limit] 0h = limit not reached 1h = limit reached
1	VCC_WARN	RC	0h	VCC under voltage warning Indicates voltage on VCC pin has decreased below undervoltage warning limit [more details on UV limit] 0h = limit not reached 1h = limit reached
0	VCC_UVLO	RC	0h	VCC UVLO status Indicates voltage on VCC pin has decreased below UVLO limit [more details on UV limit] 0h = limit not reached 1h = limit reached

3.12.1.27 DEV26 Register (Offset = 1Ah) [Reset = 00h]

DEV26 is shown in Table 7-31.

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Table 7-31 DEV26 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	RESERVED	R	0h	Reserved

3.12.1.28 Extended Feature Support 0 Register (Offset = 1Bh) [Reset = 00h]

Extended Feature Support 0 is shown in Table 7-32.

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Table 7-32 Extended Feature Support 0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R	0h	Reserved
2	FH_TX_CKSM_ERR_DIS	R/W	0h	Disable Frame Handler TX Checksum Error 0h = checksum error detection enabled 1h = checksum error detection disabled
1	FH_T1_TA_T2_DIS	R/W	0h	Disable Frame Handler T1, TA and T2 Timeouts 0h = timeout detection enabled 1h = timeout detection disabled
0	TRX_ERR_DIS	R/W	0h	Disable Transmission Error Check 0h = transmission error detection enabled 1h = transmission error detection disabled

3.12.1.29 Extended Feature Support 1 Register (Offset = 1Ch) [Reset = 00h]

Extended Feature Support 1 is shown in Table 7-33.

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Table 7-33 Extended Feature Support 1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	HSSB_TSC_DIS	R/W	0h	HSSB Blanking Time Disable 0h = blanking time enabled 1h = blanking time disabled
6	LPB_TSC_DIS	R/W	0h	LPB Blanking Time Disable 0h = blanking time enabled 1h = blanking time disabled
5	CQB_TSC_DIS	R/W	0h	CQB Blanking Time Disable 0h = blanking time enabled 1h = blanking time disabled
4	EXTD_COM_B	R/W	0h	Channel B Extended COM Rate Support Enable 0h = extended COM rate support enabled 1h = extended COM rate support disabled
3	HSSA_TSC_DIS	R/W	0h	HSSA Blanking Time Disable 0h = blanking time enabled 1h = blanking time disabled
2	LPA_TSC_DIS	R/W	0h	LPA Blanking Time Disable 0h = blanking time enabled 1h = blanking time disabled
1	CQA_TSC_DIS	R/W	0h	CQA Blanking Time Disable 0h = blanking time enabled 1h = blanking time disabled
0	EXTD_COM_A	R/W	0h	Channel A Extended COM Rate Support Enable 0h = extended COM rate support enabled 1h = extended COM rate support disabled

3.12.1.30 CQ Driver Max Auto Recovery Register (Offset = 1Dh) [Reset = 00h]

CQ Driver Max Auto Recovery is shown in Table 7-34.

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Table 7-34 CQ Driver Max Auto Recovery Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	CQB_DRV_MAX_AR	R/W	0h	C/Q channel B driver maximum auto recovery Sets the maximum number of times the driver will attempt to recover from an overcurrent fault 0h = unlimited retries 1h = 1 retry 2h = 2 retries 3h = 3 retries 4h = 4 retries 5h = 5 retries 6h = 6 retries 7h = 7 retries 8h = 8 retries 9h = 9 retries Ah = 10 retries Bh = 11 retries Ch = 12 retries Dh = 13 retries Eh = 14 retries Fh = 15 retries
3-0	CQA_DRV_MAX_AR	R/W	0h	C/Q channel A driver maximum auto recovery Sets the maximum number of times the driver will attempt to recover from an overcurrent fault 0h = unlimited retries 1h = 1 retry 2h = 2 retries 3h = 3 retries 4h = 4 retries 5h = 5 retries 6h = 6 retries 7h = 7 retries 8h = 8 retries 9h = 9 retries Ah = 10 retries Bh = 11 retries Ch = 12 retries Dh = 13 retries Eh = 14 retries Fh = 15 retries

3.12.1.31 LP Max Auto Recovery Register (Offset = 1Eh) [Reset = 00h]

LP Max Auto Recovery is shown in Table 7-35.

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Table 7-35 LP Max Auto Recovery Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	LPB_MAX_AR	R/W	0h	L+ channel B driver maximum auto recovery Sets the maximum number of times the driver will attempt to recover from an overcurrent fault 0h = unlimited retries 1h = 1 retry 2h = 2 retries 3h = 3 retries 4h = 4 retries 5h = 5 retries 6h = 6 retries 7h = 7 retries 8h = 8 retries 9h = 9 retries Ah = 10 retries Bh = 11 retries Ch = 12 retries Dh = 13 retries Eh = 14 retries Fh = 15 retries
3-0	LPA_MAX_AR	R/W	0h	L+ channel A driver maximum auto recovery Sets the maximum number of times the driver will attempt to recover from an overcurrent fault 0h = unlimited retries 1h = 1 retry 2h = 2 retries 3h = 3 retries 4h = 4 retries 5h = 5 retries 6h = 6 retries 7h = 7 retries 8h = 8 retries 9h = 9 retries Ah = 10 retries Bh = 11 retries Ch = 12 retries Dh = 13 retries Eh = 14 retries Fh = 15 retries

3.12.1.32 HSS Max Auto Recovery Register (Offset = 1Fh) [Reset = 00h]

HSS Max Auto Recovery is shown in Table 7-36.

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Table 7-36 HSS Max Auto Recovery Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	HSSB_MAX_AR	R/W	0h	High side switch channel B driver maximum auto recovery Sets the maximum number of times the driver will attempt to recover from an overcurrent fault 0h = unlimited retries 1h = 1 retry 2h = 2 retries 3h = 3 retries 4h = 4 retries 5h = 5 retries 6h = 6 retries 7h = 7 retries 8h = 8 retries 9h = 9 retries Ah = 10 retries Bh = 11 retries Ch = 12 retries Dh = 13 retries Eh = 14 retries Fh = 15 retries
3-0	HSSA_MAX_AR	R/W	0h	High side switch channel A driver maximum auto recovery Sets the maximum number of times the driver will attempt to recover from an overcurrent fault 0h = unlimited retries 1h = 1 retry 2h = 2 retries 3h = 3 retries 4h = 4 retries 5h = 5 retries 6h = 6 retries 7h = 7 retries 8h = 8 retries 9h = 9 retries Ah = 10 retries Bh = 11 retries Ch = 12 retries Dh = 13 retries Eh = 14 retries Fh = 15 retries