SLUSG35 August   2026 TPS12S24F-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply Input
      2. 7.3.2 Charge Pump and Gate Driver Output (VS, GATEx, BSTx, SRCx)
      3. 7.3.3 Driving Capacitive, Resistive and Inductive Loads
        1. 7.3.3.1 Capacitive Load Driving
          1. 7.3.3.1.1 Using SCP Based Auto-Retry Method (GATEx):
          2. 7.3.3.1.2 Using Main Path Gate Slew Rate Control Method (GATEx, SRCx):
          3. 7.3.3.1.3 Using PWM Control Method (GATEx):
        2. 7.3.3.2 Resistive or Inductive Load Driving
      4. 7.3.4 Protection Mechanisms
        1. 7.3.4.1 I2T Based Overcurrent and Short-Circuit Protection
        2. 7.3.4.2 NTC-Based External FET Over-Temperature Protection
        3. 7.3.4.3 Device Junction Overtemperature Warning
        4. 7.3.4.4 Input Undervoltage and Overvoltage Protection
        5. 7.3.4.5 External FET Drain to Source Voltage (VDS) Overvoltage Protection
        6. 7.3.4.6 Bi-VDS Based Short-Circuit Protection
        7. 7.3.4.7 Reverse Polarity Protection
        8. 7.3.4.8 Loss of Ground
      5. 7.3.5 Diagnostic Mechanisms
        1. 7.3.5.1 ADC Sense Signals
        2. 7.3.5.2 Analog and Digital Current Monitor (VIMONx)
        3. 7.3.5.3 Input Supply Voltage Measurement
        4. 7.3.5.4 Output Voltage Measurement
        5. 7.3.5.5 External FET Temperature Measurement
        6. 7.3.5.6 External FET Bi-Directional Drain to Source (Bi-VDS) Measurement
        7. 7.3.5.7 Controller Temperature Measurement
        8. 7.3.5.8 VOUT Short-to-Battery or FET Short and Open-Load Detection
          1. 7.3.5.8.1 Measurement With Main FET (GATEx) Enabled
          2. 7.3.5.8.2 Detection With Main FET (GATEx) Disabled
        9. 7.3.5.9 VOUT Short-to-Battery or FET Short Detection For Power At All Times (PAAT) Loads
      6. 7.3.6 Fault Indication (FLT / WAKE)
      7. 7.3.7 Output Disable (OUT_DISx) Function
      8. 7.3.8 Brief Supply Interruptions Behaviour
      9. 7.3.9 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Config or Active Mode (AM)
      5. 7.4.5 Low Power Mode (LPM)
      6. 7.4.6 Limphome Mode
    5. 7.5 TPS12S24F-Q1 Pre-Production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS12S24F-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Driving Power at All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 TPS12S24F-Q1 System Level Configurations
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient and EMI/EMC Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

7.3.5.1 ADC Sense Signals

The TPS12SxxF-Q1 provides an integrated successive approximation 10-bit ADC which can convert different analog signals to digital signals which can be read out through SPI. The ADC can convert the following analog signals:

  • Channel input voltage sense available from ADC_RESULT_VBB register

  • Channel output voltage sensing available from ADC_RESULT_CHx_V register

  • External FET temperature sensing available from ADC_RESULT_CHx_T register

  • Controller Junction temperature sensing available from ADC_RESULT_TCONT register

  • Channel drain to source voltage sensing available from ADC_RESULT_CHx_VDS register

Figure 7-19 provides a functional block diagram of the integrated ADC along with the analog signal inputs to the ADC. Conversion of any of the analog signals can either be disabled globally through the ADC_CONFIG register.

TPS12S24F-Q1 TPS12SxxF-Q1 ADC Block DiagramFigure 7-19 TPS12SxxF-Q1 ADC Block Diagram

The device also provides a configurable delay which can also help to further reduce the quiescent current of the device by reducing the sampling rate of the ADC. The configurable delay is set by the ADC_CONFIG_DELAY bits in the ADC_CONFIG register.

If I2T protection is enabled (I2T_EN_CHx = 1) and either channel is not in I2T mode (I2T_MOD_CHx = 0), then the device will convert each of the analog signals in a round robin sequence with the configurable delay. Figure 7-20 below shows the ADC scheduling if no channel is in I2T mode (I2T_MOD_CHx = 0) and all analog signal conversions are enabled. If I2T protection is disabled then the round robin sequence below also applies.

If I2T protection is enabled (I2T_EN_CHx = 1) and one or both of the channels are in I2T mode (I2T_MOD_CHx = 1), then the device disables all conversions except for the ISNSx conversions which are used for the internal I2T protection. The device also disables the configurable delay function as well. Figure 7-20 below shows the ADC scheduling if one or both of the channels are in I2T mode (I2T_MOD_CHx = 1).

If any of the channels are in the I2T loop (I2T_MOD_CHx = 1), the VBB, TCONT, TSNSx, VDSx measurement, if enabled, will be disabled for all the channels and the VSNS_RDY_CHx bit will be 0. Once the channel(s) exit the I2T loop (I2T_MOD_CHx = 0), then all these measurements will be automatically re-enabled if previously enabled before the I2T event.

TPS12S24F-Q1 TPS12SxxF-Q1 ADC Conversion SequenceFigure 7-20 TPS12SxxF-Q1 ADC Conversion Sequence

The reference voltage for the ADC is fixed internally and is specified in the electrical characteristics table through the VADC_REF parameter. The ADC's ground reference is connected internally to the GND of the device.

The conversion equation for each of the analog signals can be found in their respective sections below.