SLUSG35 August   2026 TPS12S24F-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply Input
      2. 7.3.2 Charge Pump and Gate Driver Output (VS, GATEx, BSTx, SRCx)
      3. 7.3.3 Driving Capacitive, Resistive and Inductive Loads
        1. 7.3.3.1 Capacitive Load Driving
          1. 7.3.3.1.1 Using SCP Based Auto-Retry Method (GATEx):
          2. 7.3.3.1.2 Using Main Path Gate Slew Rate Control Method (GATEx, SRCx):
          3. 7.3.3.1.3 Using PWM Control Method (GATEx):
        2. 7.3.3.2 Resistive or Inductive Load Driving
      4. 7.3.4 Protection Mechanisms
        1. 7.3.4.1 I2T Based Overcurrent and Short-Circuit Protection
        2. 7.3.4.2 NTC-Based External FET Over-Temperature Protection
        3. 7.3.4.3 Device Junction Overtemperature Warning
        4. 7.3.4.4 Input Undervoltage and Overvoltage Protection
        5. 7.3.4.5 External FET Drain to Source Voltage (VDS) Overvoltage Protection
        6. 7.3.4.6 Bi-VDS Based Short-Circuit Protection
        7. 7.3.4.7 Reverse Polarity Protection
        8. 7.3.4.8 Loss of Ground
      5. 7.3.5 Diagnostic Mechanisms
        1. 7.3.5.1 ADC Sense Signals
        2. 7.3.5.2 Analog and Digital Current Monitor (VIMONx)
        3. 7.3.5.3 Input Supply Voltage Measurement
        4. 7.3.5.4 Output Voltage Measurement
        5. 7.3.5.5 External FET Temperature Measurement
        6. 7.3.5.6 External FET Bi-Directional Drain to Source (Bi-VDS) Measurement
        7. 7.3.5.7 Controller Temperature Measurement
        8. 7.3.5.8 VOUT Short-to-Battery or FET Short and Open-Load Detection
          1. 7.3.5.8.1 Measurement With Main FET (GATEx) Enabled
          2. 7.3.5.8.2 Detection With Main FET (GATEx) Disabled
        9. 7.3.5.9 VOUT Short-to-Battery or FET Short Detection For Power At All Times (PAAT) Loads
      6. 7.3.6 Fault Indication (FLT / WAKE)
      7. 7.3.7 Output Disable (OUT_DISx) Function
      8. 7.3.8 Brief Supply Interruptions Behaviour
      9. 7.3.9 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Config or Active Mode (AM)
      5. 7.4.5 Low Power Mode (LPM)
      6. 7.4.6 Limphome Mode
    5. 7.5 TPS12S24F-Q1 Pre-Production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS12S24F-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Driving Power at All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 TPS12S24F-Q1 System Level Configurations
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient and EMI/EMC Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

7.3.4.6 Bi-VDS Based Short-Circuit Protection

The drain to source voltage of activated channel(s) is continuously monitored which can also be used for VDS based short-circuit protection (SCP). The VDS based SCP protection is available in both the direction and can be enabled using VDS_PROT_EN_CHx bit along with threshold setting using combination of VDS_OVP_SET_CHx and VDS_GAIN_CHx bits. A configurable filter time set using VDS_OVP_MASK_CHx is provided for each channel independently to set masking or deglitch time in order to avoid false trip due to noisy signal measurement. Figure 7-16 shows application circuit with VDS based SCP protection without current sense resistor (RSNSx) leading to system level size and cost reduction.

With GATEx tunred on by CHx_ON bit, first VGS of external FET is sensed by monitoring the voltage across GATEx to SRCx pins. Once GATEx to SRCx voltage raises above VCHx(GATE_GOOD) (7.5V typical) threshold which ensures that the external FET is enhanced, then the VDS based protection is activated.

TPS12S24F-Q1 TPS12SxxF-Q1 VDS Based SCP Protection Aplication CircuitFigure 7-16 TPS12SxxF-Q1 VDS Based SCP Protection Aplication Circuit

Table 7-2 shows threshold setting for VDS based SCP protection based on combination of VDS_OVP_SET_CHx and VDS_GAIN_CHx[1:0] bits.

Table 7-2 Threshold Settings For VDS Based SCP Protection

VDS_OVP_SET_CHx[4:0]

VDS OVP THRESHOLD (mV)

VDS_GAIN_CHx[1:0] =

'01'

'10'

'11'

0

300

56

15

1

340

64

17

2

380

72

19

3

425

80

21

4

465

87.5

24

5

510

95

26

6

550

105

28

7

590

110

30

8

635

120

32

9

675

126.5

34

10

715

135

36

11

760

142.5

38

12

800

150

40

13

840

158

42

14

880

165

44

15

925

175

46

16

965

182

48

17

1010

190

50

18

1050

197

52

19

1090

205

54

20

1130

212.5

56

21

1175

220

58

22

1215

230

61

23

1260

236

63

24

1300

245

65

25

1340

252

67

26

1385

260

69

27

Reserved

267.5

71

28

Reserved

275

73.5

29

Reserved

283

75

30

Reserved

290

77.5

31

Reserved

300

80