SLUSG35 August   2026 TPS12S24F-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply Input
      2. 7.3.2 Charge Pump and Gate Driver Output (VS, GATEx, BSTx, SRCx)
      3. 7.3.3 Driving Capacitive, Resistive and Inductive Loads
        1. 7.3.3.1 Capacitive Load Driving
          1. 7.3.3.1.1 Using SCP Based Auto-Retry Method (GATEx):
          2. 7.3.3.1.2 Using Main Path Gate Slew Rate Control Method (GATEx, SRCx):
          3. 7.3.3.1.3 Using PWM Control Method (GATEx):
        2. 7.3.3.2 Resistive or Inductive Load Driving
      4. 7.3.4 Protection Mechanisms
        1. 7.3.4.1 I2T Based Overcurrent and Short-Circuit Protection
        2. 7.3.4.2 NTC-Based External FET Over-Temperature Protection
        3. 7.3.4.3 Device Junction Overtemperature Warning
        4. 7.3.4.4 Input Undervoltage and Overvoltage Protection
        5. 7.3.4.5 External FET Drain to Source Voltage (VDS) Overvoltage Protection
        6. 7.3.4.6 Bi-VDS Based Short-Circuit Protection
        7. 7.3.4.7 Reverse Polarity Protection
        8. 7.3.4.8 Loss of Ground
      5. 7.3.5 Diagnostic Mechanisms
        1. 7.3.5.1 ADC Sense Signals
        2. 7.3.5.2 Analog and Digital Current Monitor (VIMONx)
        3. 7.3.5.3 Input Supply Voltage Measurement
        4. 7.3.5.4 Output Voltage Measurement
        5. 7.3.5.5 External FET Temperature Measurement
        6. 7.3.5.6 External FET Bi-Directional Drain to Source (Bi-VDS) Measurement
        7. 7.3.5.7 Controller Temperature Measurement
        8. 7.3.5.8 VOUT Short-to-Battery or FET Short and Open-Load Detection
          1. 7.3.5.8.1 Measurement With Main FET (GATEx) Enabled
          2. 7.3.5.8.2 Detection With Main FET (GATEx) Disabled
        9. 7.3.5.9 VOUT Short-to-Battery or FET Short Detection For Power At All Times (PAAT) Loads
      6. 7.3.6 Fault Indication (FLT / WAKE)
      7. 7.3.7 Output Disable (OUT_DISx) Function
      8. 7.3.8 Brief Supply Interruptions Behaviour
      9. 7.3.9 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Config or Active Mode (AM)
      5. 7.4.5 Low Power Mode (LPM)
      6. 7.4.6 Limphome Mode
    5. 7.5 TPS12S24F-Q1 Pre-Production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS12S24F-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Driving Power at All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 TPS12S24F-Q1 System Level Configurations
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient and EMI/EMC Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

Low Power Mode (LPM)

The device transitions from ACTIVE to low power mode (LPM) whenever LPM_ENTRY bit is set to '1'. In LPM, charge pump is enabled with main FET (GATEx) OFF and bypass FET ON and FLT/WAKE pin asserted high in this mode.

The device features two types of loadwakeup mechanism described in subsequent sections

Automatic Low Power Mode (LPM) to Active Mode (AUTO_LPM_ENTRY = '0'):

When the device is in low power mode (LPM), LPM_STATUS bit is set '1'. The device transitions from LPM to active mode automatically whenever load current (ICHx(LOAD)) exceeds load wakeup trigger threshold (ICHx(LWUx)) setting configured in LPM_EXIT_CURR_CHx. After load current exceeds load wakeup threshold, device automatically turns ON the main FET (GATEx) first and bypass FET is turned OFF after main FET (GATEx) has fully turned ON and and FLT/WAKE pin asserts low indicating the exit from the LPM. LPM_WAKE_CHx bit is also set to '1' in register map and LPM_STATUS bit is also reset to '0'.

Load wakeup deglitch time can be selected in LOAD_WAKE_DEGLITCH setting. AUTO LPM feature has to be disabled by resetting AUTO_LPM_ENTRY bit to '0'.

The device features short-circuit current protection in LPM. If the voltage between VBBx to SRCx exceeds VCHx(LPM_SCP) threshold then bypass FET is turned OFF in nanoseconds and main FET (GATEx) is turned ON within tLPM_SC time along with FLT/WAKE pin asserted low. LPM_HS_CHx bit is set to '1' in order to indicate short-circuit in low power mode which can be read by MCU over SPI.

TPS12S24F-Q1 Timing Diagram for Loadwakeup and VOUT Shorted to Ground Fault in LPMFigure 7-33 Timing Diagram for Loadwakeup and VOUT Shorted to Ground Fault in LPM

Automatic Low Power Mode (LPM) to Active Mode to LPM (AUTO LPM) for ECU polling (AUTO_LPM_ENTRY = '1'):

The TPS12SxxF-Q1 has integrated AUTO LPM feature which can be enabled by AUTO_LPM_ENTRY bit in DEV_CONFIG register. AUTO LPM functionality provides flexibility for the device to automatically transition from active to a low IQ LPM while keeping power available to output at all times.

If AUTO_LPM_ENTRY bit is set to '1' and loadwakeup is detected by device (ICHx(LOAD) > ICHx(LWUx)) then device starts internal timer (tLPM_WAKE_DEGLITCH) based on LPM_WAKE_DEGLITCH timer setting in LPM register. After the 500us (current sense amplifier startup and settling time), device sense VSNSx (ICHx(LOAD) x RSNSx) voltage through CSx+ and CSx- pin and starts comparing VSNSx with fixed VCHx(AUTO_LPM_THS) (1mV typical) threshold.

EVENT1: If sensed VSNSx goes below VCHx(AUTO_LPM_THS) within LPM_WAKE_DEGLITCH timer and VSNSx stays below VCHx(AUTO_LPM_THS) threshold for AUTO_LPM_FILTER setting then device automatically transitions to LPM by turning on the bypass FET and then turning off the main path (GATEx drive). FLT / WAKE is not asserted and remains high.

NOTE: It is recommended to set LPM_WAKE_DEGLITCH time more than loadwakeup current pulse time + AUTO_LPM_FILTER setting otherwise device will stay in active mode and not transition to LPM automatically.

EVENT2: If sensed VSNSx stays above VCHx(AUTO_LPM_THS) within LPM_WAKE_DEGLITCH timer setting then device remains in active mode with the main path on (GATEx drive). FLT/WAKE is asserted low in order to indication WAKE to the MCU. MCU can reset LPM_ENTRY bit to '0' in order to de-assert the FLT/WAKE pin to high.

EVENT3: LPM_WAKE_DEGLITCH and AUTO_LPM_FILTER setting is only enabled when load wakeup is detected. These settings are disabled when FLT/WAKE is asserted low once.

The device features short-circuit current protection in LPM. If the voltage between VBBx to SRCx exceeds VCHx(LPM_SCP) threshold then bypass FET is turned OFF in nanoseconds and main FET (GATEx) is turned ON within tLPM_SC time along with FLT/WAKE pin asserted low as shown in above image as EVENT 2. LPM_HS_CHx bit is set to '1' in order to indicate short-circuit in low power mode which can be read by MCU over SPI.

TPS12S24F-Q1 Timing Diagram For Loadwakeup With Automatic LPM Entry For ECU PollingFigure 7-34 Timing Diagram For Loadwakeup With Automatic LPM Entry For ECU Polling