SLUSG35 August   2026 TPS12S24F-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply Input
      2. 7.3.2 Charge Pump and Gate Driver Output (VS, GATEx, BSTx, SRCx)
      3. 7.3.3 Driving Capacitive, Resistive and Inductive Loads
        1. 7.3.3.1 Capacitive Load Driving
          1. 7.3.3.1.1 Using SCP Based Auto-Retry Method (GATEx):
          2. 7.3.3.1.2 Using Main Path Gate Slew Rate Control Method (GATEx, SRCx):
          3. 7.3.3.1.3 Using PWM Control Method (GATEx):
        2. 7.3.3.2 Resistive or Inductive Load Driving
      4. 7.3.4 Protection Mechanisms
        1. 7.3.4.1 I2T Based Overcurrent and Short-Circuit Protection
        2. 7.3.4.2 NTC-Based External FET Over-Temperature Protection
        3. 7.3.4.3 Device Junction Overtemperature Warning
        4. 7.3.4.4 Input Undervoltage and Overvoltage Protection
        5. 7.3.4.5 External FET Drain to Source Voltage (VDS) Overvoltage Protection
        6. 7.3.4.6 Bi-VDS Based Short-Circuit Protection
        7. 7.3.4.7 Reverse Polarity Protection
        8. 7.3.4.8 Loss of Ground
      5. 7.3.5 Diagnostic Mechanisms
        1. 7.3.5.1 ADC Sense Signals
        2. 7.3.5.2 Analog and Digital Current Monitor (VIMONx)
        3. 7.3.5.3 Input Supply Voltage Measurement
        4. 7.3.5.4 Output Voltage Measurement
        5. 7.3.5.5 External FET Temperature Measurement
        6. 7.3.5.6 External FET Bi-Directional Drain to Source (Bi-VDS) Measurement
        7. 7.3.5.7 Controller Temperature Measurement
        8. 7.3.5.8 VOUT Short-to-Battery or FET Short and Open-Load Detection
          1. 7.3.5.8.1 Measurement With Main FET (GATEx) Enabled
          2. 7.3.5.8.2 Detection With Main FET (GATEx) Disabled
        9. 7.3.5.9 VOUT Short-to-Battery or FET Short Detection For Power At All Times (PAAT) Loads
      6. 7.3.6 Fault Indication (FLT / WAKE)
      7. 7.3.7 Output Disable (OUT_DISx) Function
      8. 7.3.8 Brief Supply Interruptions Behaviour
      9. 7.3.9 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Config or Active Mode (AM)
      5. 7.4.5 Low Power Mode (LPM)
      6. 7.4.6 Limphome Mode
    5. 7.5 TPS12S24F-Q1 Pre-Production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS12S24F-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Driving Power at All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 TPS12S24F-Q1 System Level Configurations
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient and EMI/EMC Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

7.3.4.1 I2T Based Overcurrent and Short-Circuit Protection

The device includes a programmable fuse protection for each channel, that is based on a defined time-current curve and is commonly referred to as I2T protection in melting fuse data sheets. The intent is to match the switch turnoff behavior of a melting fuse. The NOM_CUR_CHx bits and I2T_TRIP_CHx bits set the time-current curve and immediate shutdown protection (ISC) to create the full I2T protection for the device. The I2T protection of the device consists of three regions:

The I2T protection of the device consists of three regions:

  1. Nominal current

  2. I2T based Fuse shutdown

  3. Immediate shutdown protection (SCP)

The operational region for the fuse-based shutdown is shown in the Figure below. Exemplary values for the current values that bound the operational region is included.

TPS12S24F-Q1 Configurable Current vs Time Characteristics Curve For TPS12SxxF-Q1 Figure 7-10 Configurable Current vs Time Characteristics Curve For TPS12SxxF-Q1

The nominal current region (1) defines the region where the device can supply current indefinitely without turning off. This is roughly equivalent to the fuse current rating of a melting fuse. This region is set by the NOM_CUR_CHx bits and if the output current is less than the NOM_CUR_CHx setting then the device can supply current indefinitely as previously stated and it will not start the I2T accumulation. If the output current is greater than or equal to the NOM_CUR_CHx setting then the device will enter the I2T accumulation loop and will start to accumulate until the I2T_TRIP_CHx threshold is met. If the output current falls back below the NOM_CUR_CHx before the I2T_TRIP_CHx value is reached then the device will start the I2T de-accumulation.

Above the nominal current region, is the fuse shutdown region (2) which is set by the I2T_TRIP_CHx bits. This region defines the curvature of time-current curve and the region where the I2T accumulation of the device is active and where I2T_MOD_CHx is set to 1. Based on the output current level and the NOM_CUR_CHx setting the device will trip at different time intervals based on the I2T_TRIP_CHx value that is set. Depending on the DCR_CHx bit in the I2T_CONFIG_CHx register, the time-current curve of the device is defined by the below equations:

I2T Accumulation and De-accumulation for DCR_CHx = '0' setting:

I2T_TRIP = (ILOAD2) * t (Equation 1)

For DCR_CHx = 0, the device also offers a configurable decrement factor through the ACC_DCR0_CHx bits in the I2T_CONFIG_CHx register which can vary the decrement time for DCR_CHx = 0.

TPS12S24F-Q1 I2T Accumulation and De-Accumulation With DCR_CHx = '0' Setting Figure 7-11 I2T Accumulation and De-Accumulation With DCR_CHx = '0' Setting

I2T Accumulation and De-accumulation for DCR_CHx = '1' setting:

I2T_TRIP = (ILOAD2 − INOM2) * t (Equation 2)

Depending on the DCR_CHx setting, the I2T_TRIP_CHx bits in the I2T_CONFIG_CHx will have different thresholds. For more information on the I2T trip thresholds, see the I2T_CONFIG_CHx register.

TPS12S24F-Q1 I2T Accumulation and De-Accumulation With DCR_CHx = '1' Setting Figure 7-12 I2T Accumulation and De-Accumulation With DCR_CHx = '1' Setting

If the accumulation does not exceed the I2T_TRIP_CHx value and the current falls below NOM_CUR_CHx then equation 1 or equation 2 depending on the DCR_CHx setting is used to decrement the accumulated energy based on the ISNSx value until it reaches zero. While the device continues to decrement down to zero, the I2T_MOD_CHx bit will remain 1 until accumulated energy returns back to zero and then the I2T_MOD_CHx bit will be set back to zero. If any conversions were disabled due to a channel entering the I2T loop then they will be re-enabled when I2T_MOD_CHx = 0.

If a shutdown occurs either due to the I2T_TRIP_CHx value then, the device will remain off for a period set by the TCLDN_CHx. If the TCLDN_CHx = 00 then the device will remain in latch off and will not retry.

The immediate shutdown overcurrent protection (SCP) region (3) is set by the FWD_SCP_SET_CHx and REV_SCP_SET_CHx bits. If the output current exceeds the ISC level then the device will turn off immediately. The retry or latched off behavior for the SCP is set by the LATCH_CHx bit and discussed in the auto-retry and latch-off operation section.

The device also features I2T accumulation in reverse direction as shown in below figure. The accumulation is not reset at crossover point (zero load current) whenever load current flows from one direction to another and remains above INOM current threshold.

TPS12S24F-Q1 I2T Accumulation and De-Accumulation During Forward and Reverse Load Current Flow Figure 7-13 I2T Accumulation and De-Accumulation During Forward and Reverse Load Current Flow