The TPS12SxxF-Q1 communicates with the host controller through a high-speed SPI serial interface. The interface has three logic inputs: clock (SCLK), chip select (CS), serial data in (SDI), and one data out (SDO). The SDO is tri-stated when the CS pin is high. The maximum SPI clock rate is 10MHz, but is limited in practice by the series protection resistor. The device supports simple daisy chain SPI. This mode can be used with or without CRC. The communication between the TPS12SxxF-Q1 and the controller or MCU is through a SPI bus in a primary-secondary configuration. The external MCU is always an SPI primary device that sends command requests on the SDI pin of the TPS12SxxF-Q1 and receives device responses on the SDO pin of the device. The TPS12SxxF-Q1 device is always an SPI secondary device that receives command requests over the SDI line and sends responses (such as status and measured values) to the external MCU over the SDO line. The TPS12SxxF-Q1 device can be connected to the primary MCU in the following formats:

Figure 7-25 Independent Secondary Configuration (Separate nCS Signal)

Figure 7-26 Daisy Chain Configuration

SPI Interface:

The SPI interface pin behavior is described in this section.

Chip Select ( CS):

The system microcontroller selects the TPS12SxxF-Q1 to receive communication using the CS pin. With the CS pin in a logic LOW state, command/configuration words may be sent to the TPS12SxxF-Q1 via the serial input (SDI) pin, and the device information can be retrieved by the microcontroller via the serial output (SDO) pin. The falling edge of the CS enables the SDO output and latches the content of the FAULT_GLOBAL register that will be sending out on SDO. The microcontroller may issue a READ command to retrieve information stored in the registers. The rising edge on the CS pin initiates the following actions: 1. Addressed registers are updated if there is no SPI communication error and if it is an SPI write command. 2. Read clear register is cleared if a READ command to this register was issued during CS = LOW. To avoid any corrupted data, it is essential the HIGH-to-LOW and LOW-to-HIGH transitions of the CS signal occur only when SCLK is in a logic LOW state. A clean CS signal is needed to ensure no incomplete SPI words are sent to the device. This pin is internally pulled up to the VDD rail.

System Clock (SCLK):

The system clock (SCLK) pin clocks the internal shift register of the TPS12SxxF-Q1. The SDI data is latched into the input shift register on the falling edge of the SCLK signal. The SDO pin shifts the device stored information out on the rising edge of SCLK. The SDO data is available for the microcontroller to read on the falling edge of SCLK. False clocking of the shift register must be avoided to ensure validity of data and it is essential the SCLK pin be in a logic LOW state whenever CS pin makes any transition. Therefore, it is recommended that the SCLK pin gets pulled to a logic LOW state as long as the device is not accessed and the CS pin is at a logic HIGH state. When the CS is in a logic HIGH state, any signal on the SCLK and SDI pins will be ignored and the SDO pin remains as a high impedance output.

Serial Data In (SDI) and Serial Data Out (SDO):

The SDI pin is used for serial instruction data input. SDI information is latched into the input shift register on the falling edge of the SCLK when CS is low. The SDO pin is the output from the internal shift register. This pin is internally pulled up to the VDD rail. SDO pin is high impedance when the CS pin is high. Each successive rising SCLK edge makes the next data bit available for the microcontroller to read on the falling edge of SCLK. SDO will go back to high-impedance when CS is high.

CRC Error Detection and Checking of Clocks:

Setting the CRC_EN bit high enables CRC error detection. A CRC-4-ITU-Normal Check Sequence (FCS) is then sent along with each serial transaction. The 4-bit CRC is based on the normal generator polynomial X4+X+1 with CRC starting value = 1111. When CRC is enabled, the TPS12SxxF-Q1 expects a check byte appended to the SDI program/configure data that it receives. To program a complete word, exact bits of information (shown in following table) must be enter into the device. When CRC is disabled, the IC enables register write only if exactly bits have been clocked in. When CRC is enabled, the IC enables register write only if exactly bits have been clocked in with no CRC errors. In case the word length exceeds or does not meet the required length or there is CRC errors, the SPI_ERR bit in the FAULT_GLOBAL register is asserted to logic “1”,and the data received is considered invalid. Note the SPI_ERR bit is not flagged if SCLK is not present. The SPI_ERR will be sent back to SPI Main device on SDO during next chip access. Note that clear on read applies only when there is no SPI error when the register is read.

SPI Frame Format

The device uses a 24-bit frame width (when CRC is not used) with the format as shown in Figure 7-27. Please note that the 16-bit wide "Data Out" in the SDO output is always for the previous SPI command frame (Read or Write).

Figure 7-27 24-Bit Read, No CRC (CRC_EN=0)

Figure 7-28 24-Bit Write, No CRC (CRC_EN=0)

Figure 7-29 32-Bit Read, CRC Enabled (CRC_EN=1)

Figure 7-30 32-Bit Write, CRC Enabled (CRC_EN=1)

SPI Watchdog Function:

The TPS12SxxF-Q1 device offers an optional SPI watchdog function to monitor for valid SPI transactions from the host controller and loss of the VDD supply. If a valid SPI transaction does not occur in the configurable timeout period, WD_TO, then the FLT/WAKE pin will go low and the WD_ERR bit in the FAULT_GLOBAL register will be set to '1'. A valid SPI transaction consists of a SPI transaction with no SPI errors and/or CRC errors (if enabled). If the VDD supply to the device drops below the VDD_UVLO threshold then SPI on the device is not operational. If the VDD supply remains below the VDD_UVLO for longer than the watchdog time period, then the device will issue a watchdog error where the WD_ERR bit will be set to 1 and the FLT/WAKE pin will go low unless masked.

The watchdog function is enabled through WD_EN bit in the DEV_CONFIG register. Table below showcases the different configurable watchdog timeout windows, WD_TO.