SLUSG35 August   2026 TPS12S24F-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply Input
      2. 7.3.2 Charge Pump and Gate Driver Output (VS, GATEx, BSTx, SRCx)
      3. 7.3.3 Driving Capacitive, Resistive and Inductive Loads
        1. 7.3.3.1 Capacitive Load Driving
          1. 7.3.3.1.1 Using SCP Based Auto-Retry Method (GATEx):
          2. 7.3.3.1.2 Using Main Path Gate Slew Rate Control Method (GATEx, SRCx):
          3. 7.3.3.1.3 Using PWM Control Method (GATEx):
        2. 7.3.3.2 Resistive or Inductive Load Driving
      4. 7.3.4 Protection Mechanisms
        1. 7.3.4.1 I2T Based Overcurrent and Short-Circuit Protection
        2. 7.3.4.2 NTC-Based External FET Over-Temperature Protection
        3. 7.3.4.3 Device Junction Overtemperature Warning
        4. 7.3.4.4 Input Undervoltage and Overvoltage Protection
        5. 7.3.4.5 External FET Drain to Source Voltage (VDS) Overvoltage Protection
        6. 7.3.4.6 Bi-VDS Based Short-Circuit Protection
        7. 7.3.4.7 Reverse Polarity Protection
        8. 7.3.4.8 Loss of Ground
      5. 7.3.5 Diagnostic Mechanisms
        1. 7.3.5.1 ADC Sense Signals
        2. 7.3.5.2 Analog and Digital Current Monitor (VIMONx)
        3. 7.3.5.3 Input Supply Voltage Measurement
        4. 7.3.5.4 Output Voltage Measurement
        5. 7.3.5.5 External FET Temperature Measurement
        6. 7.3.5.6 External FET Bi-Directional Drain to Source (Bi-VDS) Measurement
        7. 7.3.5.7 Controller Temperature Measurement
        8. 7.3.5.8 VOUT Short-to-Battery or FET Short and Open-Load Detection
          1. 7.3.5.8.1 Measurement With Main FET (GATEx) Enabled
          2. 7.3.5.8.2 Detection With Main FET (GATEx) Disabled
        9. 7.3.5.9 VOUT Short-to-Battery or FET Short Detection For Power At All Times (PAAT) Loads
      6. 7.3.6 Fault Indication (FLT / WAKE)
      7. 7.3.7 Output Disable (OUT_DISx) Function
      8. 7.3.8 Brief Supply Interruptions Behaviour
      9. 7.3.9 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Config or Active Mode (AM)
      5. 7.4.5 Low Power Mode (LPM)
      6. 7.4.6 Limphome Mode
    5. 7.5 TPS12S24F-Q1 Pre-Production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS12S24F-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Driving Power at All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 TPS12S24F-Q1 System Level Configurations
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient and EMI/EMC Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

7.5 TPS12S24F-Q1 Pre-Production Silicon Limitations

Table 7-9 Summary of Pre-production silicon limitations

PARAMETER

TEST CONDITION/EXPLANATION

OBSERVATION IN PRE-PRODUCTION SILICON

EXPECTED BEHAVIOR. TO BE FIXED IN PRODUCTION SILICON

Current sense Accuracy

VSNSx = 6mV,

GAINx setting = 50V/V

VIMONx pin voltage = 243.5mV

ISNS register value: ADC_RESULT_CHx_I = 87

ISNS accuracy is 12%

VIMONx pin voltage = 275mV

ISNS register value: ADC_RESULT_CHx_I = 101

ISNS digital sense accuracy should be (7%) .

I2T accuracy directly impact by ISNS accuracy.

SCP in LPM

Output Short to ground in LPM. Bypass FET turn off instantly and main FET turn on

LPM bypass FET Thermal shutdown bit goes ‘1’

LPM_HS_CHx bit remains ‘0’

LPM bypass FET Thermal shutdown remains ‘0’

LPM_HS_CHx bit should go to ‘1’

Functionality is working but wrong indication

WAKE Indication

•

Gate going high within 7.5us after loadwakeup detection but FLT/WAKE pin goes low after 50usec

FLT/WAKE pin goes low after 5usec.

No major impact at system level

GLOBAL_ERR_FLT register read

Observed only after LPM Exit

Working normally in active mode

VBB_UV_WRN = ‘1’

GLOBAL_ERR = ‘1’

VBB_UV_WRN = ‘0’

GLOBAL_ERR = ‘0’

No major impact at system level.

SDO pin state

CSn pulled low to high

SDO retains LSB of last data value. Cannot support parallel SPI interface.

SDO should be tri-state when CSn is pulled low to high.

GND Loss Detection

Device GND floating or high slew rate transient (10V/us) lifting GND pin >2V threshold

Gate turns off. Digital gets stuck (SPI Write does not work) because internal oscillator is susceptible to high slew rate on GND which can happen due to poor grounding or hot-swapping

The GATEx should turn off. GATEx should turn on automatically when GND is restored and SPI Write/Read works normally.

Charge pump UVLO

CPUVLO falling threshold

8V. Device may detect CPUVLO during FET turn off if CBSTx is not sized properly.

Should be 6.5V.

Use CBST > 10 x [Ciss (external FET) + CGATEx]

FET Short BIST

Run FET short BIST on CH1 and CH2

FET Short BIST indication works only for CH2.

FET Short BIST indication should works for CH1 and CH2.