SLUSG35 Data sheet

SLUSG35 August 2026 TPS12S24F-Q1

ADVANCE INFORMATION

7.3.6 Fault Indication (FLT / WAKE)

The device provides enhanced fault reporting through a FLT/WAKE status pin and fault status bits through SPI. The FLT/WAKE status pin allows the device to interrupt the system when a fault has occurred on the device. The FLT/WAKE status pin is an open drain output that asserts low when a fault occurs on the device. For faults which are read clear, the FLT/WAKE pin will go high if the fault no longer exists and the specific register to clear the fault is read. Indication on the FLT/WAKE pin can be masked for some faults through FAULT_MASK register. See the FAULT_MASK register for more details.

The device also provides fault information through SPI through a global fault register (FAULT_GLOBAL) and channel specific fault registers (FLT_STAT_CHx) to enable the system to quickly diagnose what caused the fault in the device. The device outputs the FAULT_GLOBAL [15:8] bits on the SDO header so these status bits can be continuously read in each SPI transaction.For more details on each of the individual fault status bits see the FAULT_GLOBAL and FLT_STAT_CHx registers in the register map.

When the device is in low power mode no fault information is available through the FLT/WAKE pin. If short circuit were to occur in LPM the device would protect itself then transition to ACTIVE mode and then will signal fault on the FLT/WAKE pin and in the fault status registers.

Table highlights how the device signals different events through the FLT/WAKE pin and the fault status bits.

Table 7-5 Fault Reporting

EVENT / FAULT	DETECTION	PROTECTION (Gate drives turned OFF)	BIT FIELD NAME IN FAULT_GLOBAL REGISTER	BIT FIELD NAME IN FLT_STAT_CHx Register	OPTIONAL INDICATION ON FLT/WAKE PIN	BIT FIELD NAME IN FAULT_MASK REGISTER
Input supply (VBB) UVLO	Yes	Yes	VBB_UVLO and GLOBAL_ERR_WRN		Yes unless masked	MASK_VBB_UVLO
Input supply (VBB) UVLO warning (V_(CSx+)< 6V)	Yes	No	VBB_UV_WRN and GLOBAL_ERR_WRN		No	-
VDD UVLO	Yes	No	VDD_UVLO	-	Yes unless masked	MASK_VDD_UVLO
SPI Watchdog error	Yes	Transition to Limphome mode	WD_ERR		Yes unless masked	MASK_WD_ERR
SPI CRC/frame error	Yes	No	SPI_ERR		Yes unless masked	MASK_SPI_ERR
NVM CRC ERROR	Yes	Yes	NVM_CRC_ERR in BIST_RESULT register		Yes unless masked	MASK_NVM_CRC_ERR
POR	Yes	Yes	POR		Yes
Off state Open load fault	Yes	No	OL_SHRT_VBB_OFF_FLT and CHx_FLT	OL_OFF_CHx	Yes unless masked	MASK_OL_OFF
VOUT short to VBB fault	Yes	No	OL_SHRT_VBB_OFF_FLT and CHx_FLT	SHRT_VBB_CHx	Yes unless masked	MASK_SHRT_VBB
External FET Over-Temperature (TSD) Shutdown	Yes	Yes	CHAN_OCP_I2T_TSD_OV and CHx_FLT	THERMAL_SD_CHx	Yes unless masked	MASK_TSD
Bypass FET Over-Temperature Shutdown	Yes	Bypass FET turned OFF Main FET turns ON	CHx_FLT	THERMAL_SD_BYP_CHx	Yes	-
Chip (controller) over temperature warning	Yes	No		THERMAL_WRN_CHx	Yes unless masked	TSD_CONT_FLT_EN bit in in DEV_CONFIG_2 register
Overvoltage on VBB	Yes	Yes	CHAN_OCP_I2T_TSD_OV		Yes unless masked	MASK_VBB_OVLO
VOUT shorted to ground (SCP)	Yes	Yes	CHAN_OCP_I2T_TSD_OV and CHx_FLT	OCP_CHx	Yes unless masked	MASK_OCP
I2T Protection	Yes	Yes	CHAN_OCP_I2T_TSD_OV and CHx_FLT	I2T_FLT_CHx	Yes unless masked	MASK_I2T_TRIP
Reverse battery (Reverse Polarity)	Yes	Yes			Yes unless masked	MASK_REV_POL_FLT
Charge pump undervoltage	Yes	Yes	CHx_FLT	CPUMP_UVLO_CHx	Yes unless masked	MASK_CPUMP_UVLO
Loss of device GND	Yes	Yes	No		No	-
Main FET (GATEx) ON/OFF after inrush duration	Yes	No	-	VOUT_ERR_CHx	No	-
Load wakeup	Yes	No	CHx_FLT	LPM_WAKE_CHx	Yes (Always available)
VOUT short to ground in LPM	Yes	Bypass FET turned OFF Main FET turns ON	CHx_FLT	LPM_HS_CHx	Yes unless masked	MASK_LPM_HS
VDS overvoltage fault	Yes	Yes	CHx_FLT	VDS_FLT_CHx	Yes unless masked	MASK_VDS_FAULT
Main FET (GATEx) ON/OFF status	Yes	No	SW_STATE_M_CH1 in SW_STATE register		No
Limphome indication	Yes	Transition to Limphome mode	LIMPHOME_STAT		Yes unless masked	LIMPHOME_STAT_FLT_EN bit in DEV_CONFIG_3 register
OUT_DISx Indication	Yes	Yes	SW_STATE_M_CH1 in SW_STATE register		Yes
Load current change from forward to reverse direction indication	Yes	No	ISNS_POLARITY_CHx bit in ADC_RESULT_CHx_I		Yes unless masked	ISNS_POLARITY_FLT_EN bit in DEV_CONFIG_2 register

FAULT_GLOBAL [15:8] Bits:

The TPS12SxxF-Q1 device, outputs the FAULT_GLOBAL [15:8] bits on the SDO header so these status bits can be continuously read during each SPI transaction. The FAULT_GLOBAL [15:8] bits can be configured as read clear or real-time status bits based on the FLT_LTCH_DIS bit setting in the DEV_CONFIG register. The FLT_LTCH_DIS bit however does not apply to the LPM_STATUS bit.

If FLT_LTCH_DIS = 0, then the fault bits are latched and are cleared only when the associated register in the bit description is read and the fault no longer exists. Table below highlights which registers need to be read in order to clear each of the different fault bits if the fault no longer exists. This is also detailed in each of the bit descriptions in the register map.

Table 7-6 FAULT_GLOBAL[15:8] bits

BIT	BIT NAME	REGISTER WHICH NEEDS TO BE READ TO CLEAR THE FAULT BIT IF THE FAULT NO LONGER EXISTS
15	Reserved	N/A
14	VS_POR	FAULT_GLOBAL
13	CH2_FLT	FLT_STAT_CH2
12	CH1_FLT	FLT_STAT_CH1
11	LPM_STATUS	-
10	CHAN_OCP_I2T_TSD_OV	FLT_STAT_CHx
9	I2T_MOD	FLT_STAT_CHx
8	GLOBAL_ERR_WRN	FAULT_GLOBAL

If FLT_LTCH_DIS = 1, then the fault bits will not be latched and will clear when the fault no longer exists.