SLUSG35 August   2026 TPS12S24F-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply Input
      2. 7.3.2 Charge Pump and Gate Driver Output (VS, GATEx, BSTx, SRCx)
      3. 7.3.3 Driving Capacitive, Resistive and Inductive Loads
        1. 7.3.3.1 Capacitive Load Driving
          1. 7.3.3.1.1 Using SCP Based Auto-Retry Method (GATEx):
          2. 7.3.3.1.2 Using Main Path Gate Slew Rate Control Method (GATEx, SRCx):
          3. 7.3.3.1.3 Using PWM Control Method (GATEx):
        2. 7.3.3.2 Resistive or Inductive Load Driving
      4. 7.3.4 Protection Mechanisms
        1. 7.3.4.1 I2T Based Overcurrent and Short-Circuit Protection
        2. 7.3.4.2 NTC-Based External FET Over-Temperature Protection
        3. 7.3.4.3 Device Junction Overtemperature Warning
        4. 7.3.4.4 Input Undervoltage and Overvoltage Protection
        5. 7.3.4.5 External FET Drain to Source Voltage (VDS) Overvoltage Protection
        6. 7.3.4.6 Bi-VDS Based Short-Circuit Protection
        7. 7.3.4.7 Reverse Polarity Protection
        8. 7.3.4.8 Loss of Ground
      5. 7.3.5 Diagnostic Mechanisms
        1. 7.3.5.1 ADC Sense Signals
        2. 7.3.5.2 Analog and Digital Current Monitor (VIMONx)
        3. 7.3.5.3 Input Supply Voltage Measurement
        4. 7.3.5.4 Output Voltage Measurement
        5. 7.3.5.5 External FET Temperature Measurement
        6. 7.3.5.6 External FET Bi-Directional Drain to Source (Bi-VDS) Measurement
        7. 7.3.5.7 Controller Temperature Measurement
        8. 7.3.5.8 VOUT Short-to-Battery or FET Short and Open-Load Detection
          1. 7.3.5.8.1 Measurement With Main FET (GATEx) Enabled
          2. 7.3.5.8.2 Detection With Main FET (GATEx) Disabled
        9. 7.3.5.9 VOUT Short-to-Battery or FET Short Detection For Power At All Times (PAAT) Loads
      6. 7.3.6 Fault Indication (FLT / WAKE)
      7. 7.3.7 Output Disable (OUT_DISx) Function
      8. 7.3.8 Brief Supply Interruptions Behaviour
      9. 7.3.9 SPI Mode Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 State Diagram
      2. 7.4.2 Power Down
      3. 7.4.3 Sleep Mode
      4. 7.4.4 Config or Active Mode (AM)
      5. 7.4.5 Low Power Mode (LPM)
      6. 7.4.6 Limphome Mode
    5. 7.5 TPS12S24F-Q1 Pre-Production Silicon Limitations
      1. 7.5.1 SDO Pin Tristate Discrete Workaround (Only for parallel SPI configuration not for daisy chain)
  9. 8 Register Maps
    1. 8.1 TPS12S24F-Q1 Registers
    2. 8.2 EEPROM (NVM) Overview
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Driving Power at All Times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 TPS12S24F-Q1 System Level Configurations
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient and EMI/EMC Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

9.4.1 Transient and EMI/EMC Recommendations

When the external MOSFETs turn-OFF during the conditions such as GATEx control, overcurrent or short-circuit or FET overtemperature protection causing an interruption of the current flow, the input parasitic line inductance generates a positive voltage spike on the input and output parasitic inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the input or output of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients include:

  • Use of a TVS diode and input capacitor combination across input to and GND to absorb the energy and dampen the positive transients.
  • Use of a diode or a TVS diode across the output and GND to absorb negative spikes.

Figure 9-18 shows the circuit implementation with optional protection components.

TPS12S24F-Q1 Circuit Implementation Protection Components For TPS12SxxF-Q1 Figure 9-18 Circuit Implementation Protection Components For TPS12SxxF-Q1
Table 9-2 Power Supply and EMI Recommendation Components
COMPONENT DESIGNATOR DESCRIPTION RECOMMENDED VALUE
RVS, CVS Device gets powered from the VS pin. Voltage at this pin must be maintained above V(VS_PORR) level to provide proper operation during noisy line transients. 100Ω, 1-10µF
RVDD, CVDD Voltage at this pin must be maintained above V(VDD_PORR) level to provide proper operation during noisy line transients. 4.7 to 10Ω, 1-10µF
CVBBx_BULK

Need to prevent undervoltage for device during fast output hard-short to ground fault. Place close to device CSx+ pin.

 10-100µF
CVBBx_FILTER

Need to filter out supply transients. Place close to device CSx+ pin.

 0.01-1µF
*DVBBx, *DVS, *Q3x, *Q4x

Needed for input reverse polarity protection

 Schottky diode on VS and VBBx
FB1, FB2, CCS, CCSx+, CCSx-, CVIMONx, CTMPx Ferrite beads (FB1, FB2) can be required at CSx+ ,CSx- pins for better immunity performance during EMI/EMC testing. Some other filtering is also required based on type of immunity test and frequency band through CCS, CCSx+, CCSx-, CTMPx and CVIMONx to achieve robust immunity performance. Ferrite beads should be selected such that DC Resistance is very low on CSx+ and CSx- pin to avoid significantly impacting ISNS, I2T and SCP accuracy. MMZ1608B102CTA00, 10pF for CTMPx and 10pF - 100nF for others
RGATE_PU, RGATE_PD, DGATEx, RGATEx Resistors on GATE pins can be used for controlling rise and fall time of external FETs. Separate RGATE_PU must be used for individual external FETs connected in parallel. Any value

CSRCx, CVOUTx

Limit slew rate on SRCx pin <200V/us during fast output hard-short to ground fault.

Use I = C x dV/dt for CSRCx calculation where I = Peak current, dV is max input voltage, dt = turn off time of GATEx

 0.1-10µF
RSPI All SPI or I/O pins needs to be connected to MCU or other HI/LO source through a resistor for protection transient events.

*Higher series resistor can limit SPI communication frequency so series resistor should be chosen carefully based on equivalent parasitic capacitance on SPI lines.

 100 - 500Ω

RSDO

 SDO pin needs to be connected to MCU or other HI/LO source through a resistor for protection transient events. 100 - 1000Ω

RIO, CIO

Filters out transient on LHI and DIx/OUT_DISx pins

0.01 - 10kΩ, 1-10nF

RPU

Pull up resistor

1 - 10kΩ