SLUUDM5 March 2026 MSPM0G1507 , MSPM0G1519 , MSPM0G3507 , MSPM0G3519
The following figure shows the delay components in the current measurement path.
FOC application uses DRIVER_PROPAGATION_DELAY to define the time delay in ns between the Input PWM logic edge fed to the gate driver and actual gate driver Output PWM. This delay impacts the Current Sense sampling instance on the actual gate driver output and has to be fed to the algorithm for accurate Current Sensing. Users can get the propagation delay from the used gate driver’s data sheet or measure the time with hardware.
FOC application uses DRIVER_MIN_ON_TIME to define the combined rise time and settling time of the current sense amplified output. This value has to be captured independently for a full-scale change in voltage across the current shunt. For accurate current sense reading, the current sense amplifier output to be settled before the current signal is captured. Refer to Equation 45 to calculate the DRIVER_MIN_ON_TIME.
DRIVER_MIN_ON_TIME limits the maximum FOC output PWM duty cycle to reserve sufficient time for CSA to establish the stable current signal to feed ADC sampling channel.