SNAU308A November   2024  – May 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Evaluation Setup Requirement
      2. 2.1.2 Connection Diagram
    2. 2.2 Jumper Information
    3. 2.3 Power Requirements
    4. 2.4 Reference Clock
    5. 2.5 Output Connections
    6. 2.6 Test Points
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
    3. 3.3 USB2ANY Interface
  10. 4Implementation Results
    1. 4.1 Evaluation Setup
    2. 4.2 Performance Data and Results
      1. 4.2.1 RF Output
      2. 4.2.2 VCO Calibration
        1. 4.2.2.1 No Assist Operation
        2. 4.2.2.2 Full Assist Operation
      3. 4.2.3 SYSREF
        1. 4.2.3.1 SYSREF Clock Generation
        2. 4.2.3.2 SYSREF Pulse Generation
        3. 4.2.3.3 SYSREF Repeater Mode
      4. 4.2.4 Phase Adjustment
      5. 4.2.5 Phase Synchronization
        1. 4.2.5.1 Category 1b and Category 2 SYNC
        2. 4.2.5.2 Category 3 SYNC
      6. 4.2.6 Pin Mode
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Debug Information
    2. 6.2 Trademarks
  13. 7Revision History

2.6 Test Points

Table 2-1 SPI Test Points
Test point Designator Property
TP9 SDO Serial data output (Register read back or diagnostic signal)
TP6 CSB SPI chip select input
TP7 SCK SPI clock input
TP8 SDI SPI data input
Table 2-2 Power Supply Test Point
Test point Designator Property
TP4 VCCIN 3.3V (LDO bypassed)

3.6V to 4V (use onboard LDO)
TP2 VBIAS 5V (use onboard LDO)

LMX2624SPEVM and LMX2695SEPEVM only
TP1 VCC 3.3V
TP3 GND 0V