SNAU308A November   2024  – May 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Evaluation Setup Requirement
      2. 2.1.2 Connection Diagram
    2. 2.2 Jumper Information
    3. 2.3 Power Requirements
    4. 2.4 Reference Clock
    5. 2.5 Output Connections
    6. 2.6 Test Points
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 Software Installation
    3. 3.3 USB2ANY Interface
  10. 4Implementation Results
    1. 4.1 Evaluation Setup
    2. 4.2 Performance Data and Results
      1. 4.2.1 RF Output
      2. 4.2.2 VCO Calibration
        1. 4.2.2.1 No Assist Operation
        2. 4.2.2.2 Full Assist Operation
      3. 4.2.3 SYSREF
        1. 4.2.3.1 SYSREF Clock Generation
        2. 4.2.3.2 SYSREF Pulse Generation
        3. 4.2.3.3 SYSREF Repeater Mode
      4. 4.2.4 Phase Adjustment
      5. 4.2.5 Phase Synchronization
        1. 4.2.5.1 Category 1b and Category 2 SYNC
        2. 4.2.5.2 Category 3 SYNC
      6. 4.2.6 Pin Mode
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Debug Information
    2. 6.2 Trademarks
  13. 7Revision History

4.2.3.1 SYSREF Clock Generation

To enable SYSREF function, set SYSREF_EN = 1. SYSREF operation requires some of the phase synchronization building blocks, so VCO_PHASE_SYNC must also be set to =1. When this bit is set, phase detector frequency must be equal to or less than 50MHz. Set Output MUX to SYSREF so that RFOUTB output is SYSREF clock. To generate continuous SYSREF clock, set SYSREF_REPEAT = Generation mode; set SYSREF_PULSE = Continuous mode. Clocks are coming out from RFOUTB in 20ns after the SysRefReq pin is pulled HIGH. This can be done by checking the SRREQ (pin) box. Use SYSREF divider to adjust the output SYSREF clock frequency.

LMX2624SPEVM LMX2695SEPEVM LMX2824EPEVM SYSREF Continuous Clock Generation Figure 4-20 SYSREF Continuous Clock Generation
LMX2624SPEVM LMX2695SEPEVM LMX2824EPEVM Continuous SYSREF Clock GenerationFigure 4-21 Continuous SYSREF Clock Generation
LMX2624SPEVM LMX2695SEPEVM LMX2824EPEVM SYSREF DelayFigure 4-22 SYSREF Delay

The phase between SYSREF clock (RFOUTB) and RF clock (RFOUTA) is adjustable using registers JESD_DACx.

LMX2624SPEVM LMX2695SEPEVM LMX2824EPEVM SYSREF Delay Control Figure 4-23 SYSREF Delay Control

If DC-couple of the SYSREF clock is desired, care must be taken on the output common mode voltage, which is not a constant but varied with the output voltage swing setting. Set Power to a different value changes both the SYSREF clock output voltage swing as well as the common mode voltage.

LMX2624SPEVM LMX2695SEPEVM LMX2824EPEVM SYSREF Output With Power = 2Figure 4-24 SYSREF Output With Power = 2
LMX2624SPEVM LMX2695SEPEVM LMX2824EPEVM SYSREF Output With Power = 7Figure 4-25 SYSREF Output With Power = 7