SNLA224B June   2014  – October 2025 DS90UB913A-Q1 , DS90UB954-Q1 , DS90UB960-Q1 , DS90UB9702-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Theory of Operation for Power Over Coax
    1. 2.1 Inductor Characteristics
    2. 2.2 Capacitor Characteristics
    3. 2.3 Inductors versus Ferrite Beads
  6. 3Design Considerations
    1. 3.1 Frequency Range
    2. 3.2 Power Considerations
    3. 3.3 Resistance Considerations
    4. 3.4 Inductor Size Considerations
    5. 3.5 Layout Considerations
  7. 4FPD-Link PoC Requirements
    1. 4.1 Channel Requirements
  8. 5PoC Noise
    1. 5.1 PoC Noise Requirements
    2. 5.2 Measuring VPoC Noise and Pulse
      1. 5.2.1 Requirements
      2. 5.2.2 Measurement Procedure
    3. 5.3 Measuring RIN+ Noise
      1. 5.3.1 Requirements
      2. 5.3.2 Measurement Procedures
    4. 5.4 Causes of PoC Noise
    5. 5.5 Noise Measurement Best Practices
    6. 5.6 Reducing Effects of PoC Noise
  9. 6TI Reviewed PoC Networks
    1. 6.1 PoC Network from FPD-Link III Data Sheet
    2. 6.2 Murata FPD3 Networks
      1. 6.2.1 Murata FPD3 Design 1
      2. 6.2.2 Murata FPD3 Design 2
      3. 6.2.3 Murata FPD3 Design 3
      4. 6.2.4 Murata FPD3 Design 4
      5. 6.2.5 Murata FPD3 Design 5
      6. 6.2.6 Murata FPD3 Design 6
    3. 6.3 TDK FPD3 Networks
      1. 6.3.1 TDK FPD3 Design 1
      2. 6.3.2 TDK FPD3 Design 2
      3. 6.3.3 TDK FPD3 Design 3
      4. 6.3.4 TDK FPD3 Design 4
      5. 6.3.5 TDK FPD3 Design 5
      6. 6.3.6 TDK FPD3 Design 6
      7. 6.3.7 TDK FPD3 Design 7
      8. 6.3.8 TDK FPD3 Design 8
    4. 6.4 Coilcraft FPD3 Networks
      1. 6.4.1 Coilcraft FPD3 Design 1
      2. 6.4.2 Coilcraft FPD3 Design 2
      3. 6.4.3 Coilcraft FPD3 Design 3
      4. 6.4.4 Coilcraft FPD3 Design 4
      5. 6.4.5 Coilcraft FPD3 Design 5
      6. 6.4.6 Coilcraft FPD3 Design 6
      7. 6.4.7 Coilcraft FPD3 Design 7
      8. 6.4.8 Coilcraft FPD3 Design 8
      9. 6.4.9 Coilcraft FPD3 Design 9
    5. 6.5 Murata FPD4 Networks
      1. 6.5.1  Design 1
      2. 6.5.2  Design 2
      3. 6.5.3  Design 3
      4. 6.5.4  Design 4
      5. 6.5.5  Design 5
      6. 6.5.6  Design 6
      7. 6.5.7  Design 7
      8. 6.5.8  Design 8
      9. 6.5.9  Design 9
      10. 6.5.10 Design 10
      11. 6.5.11 Design 11
      12. 6.5.12 Design 12
      13. 6.5.13 Design 13
      14. 6.5.14 Design 14
      15. 6.5.15 Design 15
      16. 6.5.16 Design 16
      17. 6.5.17 Design 17
      18. 6.5.18 Design 18
      19. 6.5.19 Design 19
      20. 6.5.20 Design 20
      21. 6.5.21 Design 21
      22. 6.5.22 Design 22
      23. 6.5.23 Design 23
      24. 6.5.24 Design 24
      25. 6.5.25 Design 25
      26. 6.5.26 Design 26
      27. 6.5.27 Design 27
      28. 6.5.28 Design 28
      29. 6.5.29 Design 29
    6. 6.6 TDK FPD4 Networks
      1. 6.6.1  Design 1
      2. 6.6.2  Design 2
      3. 6.6.3  Design 3
      4. 6.6.4  Design 4
      5. 6.6.5  Design 5
      6. 6.6.6  Design 6
      7. 6.6.7  Design 7
      8. 6.6.8  Design 8
      9. 6.6.9  Design 9
      10. 6.6.10 Design 10
      11. 6.6.11 Design 11
      12. 6.6.12 Design 12
      13. 6.6.13 Design 13
      14. 6.6.14 Design 14
      15. 6.6.15 Design 15
      16. 6.6.16 Design 16
      17. 6.6.17 Design 17
      18. 6.6.18 Design 18
      19. 6.6.19 Design 19
      20. 6.6.20 Design 20
      21. 6.6.21 Design 21
      22. 6.6.22 Design 22
      23. 6.6.23 Design 23
    7. 6.7 Coilcraft FPD4 Networks
      1. 6.7.1  Design 1
      2. 6.7.2  Design 2
      3. 6.7.3  Design 3
      4. 6.7.4  Design 4
      5. 6.7.5  Design 5
      6. 6.7.6  Design 6
      7. 6.7.7  Design 7
      8. 6.7.8  Design 8
      9. 6.7.9  Design 9
      10. 6.7.10 Design 10
      11. 6.7.11 Design 11
      12. 6.7.12 Design 12
      13. 6.7.13 Design 13
      14. 6.7.14 Design 14
      15. 6.7.15 Design 15
  10. 7Summary
  11. 8References
  12. 9Revision History

3.5 Layout Considerations

The layout of the PoC network is equally important as the network design. Due to the PoC network components making direct contact with the high-speed signal trace, good layout techniques and component placement are crucial to maintain signal integrity and remain within the insertion loss and return loss requirements. Both the high-speed channel and PoC network require tightly controlled 50Ohms (+/-10%) impedance to minimize reflections. In addition to impedance, the PCB traces need to be thick enough to support the maximum expected current load.

Place the first inductive component of the PoC network orthogonally to be barely touching the high-speed RIN+ trace. An anti-pad must be added under the first component to keep the impedance as close to 50-Ohms as possible. The anti-pad is created by adding a cut-out to the ground plane directly underneath the component’s landing pad. Since a continuous ground reference is required for the high-speed and PoC traces, the cut-out must not include any area under the connecting trace. Place the remaining PoC components close together to minimize the total footprint of the PoC network and limit 90-degree routing. For best EMI performance, do not route any high-frequency signals, including the PoC network, near the edge of the PCB board. Figure 3-1 shows an example PoC PCB layout with many of the previously described recommendations highlighted.

Example PoC Layout and Routing Figure 3-1 Example PoC Layout and Routing

Keeping the entire PoC network on the same layer as the high-speed RIN+ trace is recommended since vias can result in impedance discontinuities. However, if space constraints arise, all components other than the first inductive component can be routed to a layer other than the layer with the high-speed trace. To maintain the 50Ohm impedance, add ground reference vias near all signal vias. When sending signals between layers, care needs to be taken to avoid creating stubs. A stub is any transmission line that is only connected at one end. Stubs are commonly created by vias, routing, or through-hole connectors, which create reflections and degrade the signal quality.

For additional recommendations, refer to device datasheets.