For error-free communication between FPD-Link devices, the return loss and insertion loss on the high-speed channel must be within the limits defined by TI under worst-case current load and temperature conditions. The high-speed channel includes the serializer PCB, cable, and deserializer PCB. A PoC network is only one part of the PCB budget and overall total channel requirement. The traces on each PCB, connectors, as well as any components touching the high-speed trace can all impact loss on the channel. For this reason the layout and quality of the selected components and cables are paramount.

TI defines the channel requirements in terms of budgets for the total channel, PCB, and cable, where total channel is a combination of the PCB and cable budgets. Although meeting both the PCB and cable budgets individually is recommended, the main requirement is meeting the total channel budget. This allows for some flexibility as a PoC network that slightly violates the PCB budget, can still meet the total channel budget if a shorter or more high-quality cable is used to compensate for the additional loss. Similarly, if a lossy cable violates the cable budget, the total channel loss requirement can still be met if the PCB design results in additional margin within the PCB budget. As long as the combined PCB and cable loss is within the total channel budget, the channel specifications are considered met. However, meeting each budget with as much margin as possible is recommended. When evaluating the insertion and return loss via simulation or measurements, the system must be stressed under the maximum temperature conditions and current load.

The return loss requirement protects against signal degradation. Return loss refers to the amount of reflections in the link seen by the transmitter. A network typically fails the return loss requirement when there is an impedance mismatch in the channel. A network can also fail when inductors and ferrite beads have been chosen incorrectly. Return loss can be calculated using the following equation:

Following the FPD-Link and PoC layout guidelines from the data sheet is important to make sure the return loss requirement is met. If a board has already been designed and does not meet return loss requirements, a TDR test can be useful to help locate the area of the board where impedance mismatches occur. The return loss requirement for a FPD-Link III coax application is given in Table 4-2. For robust operation of the system, the return loss must be less than the listed values over the operating frequency range of the system. Contact TI for more information on the required Channel Specifications defined for each individual FPD-Link device and mode of operation.

Please note that the Channel Specifications document defines the loss and noise limits for each individual FPD-Link device and mode of operation. It is subject to change without notice.

Insertion loss refers to the amount of power the signal loses as the signal travels through the channel. Causes of insertion loss requirements not being met are typically due to signal attenuation in the channel and can be calculated using Equation 6.

If meeting insertion loss requirements is an issue, verify that all board layout and PoC guidelines provided by TI are being followed and high quality components are used in the signal transmission and PoC. The insertion loss requirement for a FPD-Link III coax application is given in Table 4-2. For robust operation of the system, the insertion loss must be greater than the values listed over the operating frequency range of the system. Contact TI for more information on the required Channel Specifications defined for each individual FPD-Link device and mode of operation.