Though enhancement mode GaN FETs do not contain a body diode like silicon FETs, the devices are capable of reverse conduction due to the symmetrical device structure. During the reverse conduction periods, the source-drain voltage of the integrated GaN FET is typically 2.1V, which is higher than what is encountered with a traditional silicon FET. As such, the switch node pins of the driver (SW_HS and SW_LS are externally tied together and are collectively referred to as SW) have a negative voltage present. This negative transient can lead to an excessive bootstrap voltage, since BOOT is always referenced to SW. Furthermore, the printed circuit board layout and device parasitic inductances can further intensify the negative voltage transients. The recommended implementation of the bootstrap circuity aids in reducing the likelihood of excessive negative BOOT to SW voltage. Operating at a bootstrap voltage above the absolute maximum of 16V can be detrimental to the gate driver, so care must be taken to make sure that the maximum BOOT to SW voltage differential is not exceeded. Generally, BOOT follows SW instantaneously so that the BOOT to SW voltage does not overshoot significantly. However, to further increase assurance that excessive voltage is not present at the Boot pin, an external Zener diode can be used between BOOT and SW to clamp the bootstrap voltage to acceptable values during operation.