SNOSDG7 May   2025 TPS7H6101-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Measurement
    2. 7.2 Deadtime Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gate Drive Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging Methods
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  PWM_LI and EN_HI
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode
      3. 9.2.3 Application Results
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

6.5 Electrical Characteristics

Over ambient temperature operating range TA = –55°C to 125°C, VIN = 10V to 14V, HVIN = VSW_LS = 5V, VSW_HS = GND = 0V, IDS(HS) = IDS(LS) = 1mA (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER FETs
RDS(on)(ls) Drain-source on resistance - low side VPWM_LI = 5V
ID(LS) = 2A		 TA = -55℃ 12 mΩ
TA = 25℃ 16
TA = 125℃ 24
VSD(ls) Low side source-drain (GND to SW_LS) third quadrant voltage ID(LS) = -0.5A 1.8 V
ID(LS) = -1A 2
IDSS(ls) Low side drain (SW_LS to GND) leakage current VDS(LS) = 150V
VPWM_LI = 0V		 TA = 25℃ 15 150 µA
TA = 125℃ 300
RDS(on)(hs) Drain-source on resistance - high side VEN_HI = 5V
ID(HS) = 2A		 TA = -55℃ 12 mΩ
TA = 25℃ 16
TA = 125℃ 24
VSD(hs) High side source-drain (SW_HS to HVIN) third quadrant voltage ID(HS) = 0.5A 1.8 V
ID(HS) = 1A 2
IDSS(hs) High side drain (HVIN to SW_HS) leakage current VDS(HS) = 150V
VEN_HI = 0V		 TA = 25℃ 15 150 µA
TA = 125℃ 300
SUPPLY CURRENTS
IQ_LS Low side shutdown current 
(measured on VIN)		 EN = 0V, VIN = 12V
BOOT = 10V		 MODE = PWM 5 6.8 mA
MODE = IIM 5 8
IQ_HS High side shut down current 
(measured on BOOT)		 EN = 0V
VIN = 12V
BOOT = 10V		 MODE = PWM 5 6.3 mA
EN = 0V
VIN = 12V
BOOT = 10V		 MODE = IIM 5 6.3 mA
IQ_BG BOOT to GND shutdown leakage current VSW_HS = VSW_LS = 100V, BOOT = 110V 50 µA
IOP_BG BOOT to GND operating leakage current VSW_HS = VSW_LS = 100V, BOOT = 110V 50 µA
IOP_LS Low side operating current MODE = PWM  f = 500kHz 9 12 mA
f = 1Mhz 13 16
f = 2Mhz 21 25
MODE = IIM
 		 f = 500kHz 9 12
f = 1Mhz 13 16
f = 2Mhz 21 25
IOP_HS High side operating current MODE = PWM f =500kHz 9 12 mA
f = 1Mhz 13 16
f = 2Mhz 21 25
MODE = IIM f = 500kHz 9 12
f = 1Mhz 13 16
f = 2Mhz 21 25
INTERNAL REGULATORS
VBP5L Low side 5V regulator output voltage CBP5L = 1µF 4.75 5.0 5.175 V
VBP5H High side 5V regulator output voltage CBP5H = 1µF 4.75 5.0 5.175 V
VBP7L 7V regulator output voltage CBP7L = 1µF 6.65 7 7.35 V
UNDERVOLTAGE PROTECTION
BP5HR BP5H UVLO rising threshold CBP5H = 1µF
 		 4.1 V
BP5HF BP5H UVLO falling threshold  3.9 V
BP5HH BP5H UVLO hysteresis 0.25 V
BP5LR BP5L UVLO rising threshold CBP5L = 1µF
 		 4.1 V
BP5LF BP5L UVLO falling threshold  3.9 V
BP5LH BP5L UVLO hysteresis 0.25 V
BP7LR BP7L UVLO rising threshold CBP7L = 1µF
 		 6.4 V
BP7LF BP7L UVLO falling threshold  6.1 V
BP7LH BP7L UVLO hysteresis 0.3 V
VINR VIN UVLO rising threshold 8.0 8.6 9.0 V
VINF VIN UVLO falling threshold 7.5 8.1 8.5 V
VINH VIN UVLO hysteresis 0.5 V
BOOTR BOOT UVLO rising threshold 6.6 7.1 7.4 V
BOOTF BOOT UVLO falling threshold 6.2 6.65 7 V
BOOTH BOOT UVLO hysteresis 0.45 V
INPUT PINS (EN_HI, PWM_LI)
VIR Input rising edge threshold 1.9 2.7 V
VIF Input falling edge threshold 1.20 1.85 V
VIHYS Input hysteresis 0.7 V
RPD Input pull-down resistance V = 2.15V applied at input (EN_HI or PWM_LI) 100 400 kΩ
PROGRAMMBLE DEAD TIME
tDLH Dead time low side falling to high side(1) 
 		 MODE = PWM
From VLSG = 0.48V to VHSG = 0.48V
100kHz < f ≤ 2MHz		 RLH = 35.7kΩ 20 30 37 ns
tDHL Dead time high side falling to low side(1)
 		 MODE = PWM
From VHSG = 0.48V to VLSG = 0.48V
100kHz< f ≤ 2MHz		 RHL = 57.6kΩ 36 44  53
BOOTSTRAP DIODE SWITCH
RBST_SW Bootstrap diode switch resistance IBST_SW = 100mA 0.3 Ω
Bootstrap diode switch parallel resistance IBST_RP = 1mA 0.8 1 1.2 kΩ
POWER GOOD
VPG_OL Logic-low output IFLT = 1mA 0.4 V
RPG PGOOD internal resistance BP5L = 5V, BP7L = 7V, VIN = 12V 0.6 1 1.8 MΩ
VBP7l_MIN_PG Minimum BP7L  voltage for valid PGOOD 3 3.6 V
(1) Refer to Deadtime Measurement diagram.