SNOSDG7 May   2025 TPS7H6101-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Measurement
    2. 7.2 Deadtime Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gate Drive Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging Methods
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  PWM_LI and EN_HI
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode
      3. 9.2.3 Application Results
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

5 Pin Configuration and Functions

NPR Package
64-Pin LGA
(Top View)
TPS7H6101-SEP
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
BOOT 3 I Input voltage supply of the high-side linear regulator. The external bootstrap capacitor is placed between BOOT and SW_HS. The cathode of the external bootstrap diode is connected to this pin. A Zener diode clamp between BOOT and SW_HS provides supplemental protection from exceeding the maximum electrical rating.
BP5H 58–59 P High-side 5V linear regulator output. Connect a 1μF ceramic capacitor as close as possible to the package from BP5H and SW, with a wide PCB trace connecting BP5H and PAD PB5H. When mounting on the opposite side of the PCB, position capacitor under PAD BP5H and use multiple in pad vias to minimize parasitic inductance.
BP5L 26–27 P Low-side 5V linear regulator output. Connect a 1μF ceramic capacitor as close as possible to the package from BP5L and GND, with a wide PCB trace connecting BP5L and PAD PB5L. When mounting on the opposite side of the PCB, position capacitor under PAD BP5L and use multiple in pad vias to minimize parasitic inductance.
BP7L 12 P Low-side 7V linear regulator output. A minimum of 1uF capacitance is required from BP7L to GND.
BST 11 O For bootstrap charging that utilizes the internal bootstrap switch, this pin serves as the bootstrap diode anode connection point. The external high-side bootstrap capacitor can be charged through this pin using the input voltage applied to VIN, internal bootstrap switch, and external bootstrap diode.
DLH 16 I Low-side to high-side dead time set. In PWM mode, a resistor from DLH to GND sets the dead time between the low-side turn-off and high-side turn-on. For half-bridge applications in PWM mode, connect a 35.7kΩ RDLH to GND. Alternate RDLH values can be configured, but additional testing and analysis is required to verify proper switching behavior. In independent input mode (IIM), DLH is used to configure the input interlock protection of the driver. A resistor valued between 100kΩ and 220kΩ is connected from DLH to GND for IIM with interlock enabled. DLH is connected to BP5L in IIM with interlock disabled.
DHL 15 I High-side to low-side dead time set. In PWM mode, a resistor from DHL to AGND sets the dead time between the high-side turn-off and low-side turn-on. For half-bridge applications in PWM mode, connect a 57.6kΩ RDHL to GND. Alternate RDHL values can be configured, but additional testing and analysis is required to verify proper switching behavior. In independent input mode (IIM), DHL is used to configure the input interlock protection of the driver. DHL is connected to BP5L in IIM with interlock enabled. A resistor valued between 100kΩ and 220kΩ is connected from DHL to GND for IIM with interlock disabled.
EN_HI 18 I Enable input or high-side driver control input. In PWM mode this is used as an enable pin. In independent input mode (IIM) this serves as the control input for the high-side driver.
GND 14, 21–25, 29–33, 35–40 — Low-side driver signal return. Internally connected to PAD GND 67, 68 & 70. Pins 14, 21-25, and 29 are not directly in the high current path; pins 29-33, and 35-40 are in the high current path.
HSG 57 NC High-side gate pin. This pin provides access to the gate of the high-side GaN FET for debugging and testing purposes. When configured in a half-bridge topology, connect a 10kΩ resistor from HSG to SW.
HVIN 45–50, 52–56 P Internally connected to PAD HVIN (67-68) and the high-side GaN FETs drain terminal; the pins are directly in the high current path.
LSG 28 NC Low-side gate pin. This pin provides access to the gate of the low-side GaN FET for debugging and testing purposes. When configured in a half-bridge topology, connect a 10kΩ resistor from LSG to GND.
NC1 1 NC Used to anchor the package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are solder mask defined pads; this pin is not internally connected and is recommended to be connected to the high side reference voltage (SW_LS).
NC2 2 NC No connect. This pin is not connected internally. Connection of pin NC2 to SW_HS is recommended to prevent charge buildup; however, this pin can also be left open.
NC3 20 NC Used to anchor the package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are solder mask defined pads; this pin is not internally connected and is recommended to be connected ground (GND) to prevent charge build up; however this pin can also be left open.
NC4 34 NC Used to anchor the the package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are solder mask defined pads; this pin is not internally connected and is recommended to be connected ground (GND) to prevent charge build up; however this pin can also be left open.
NC5 51 NC Used to anchor the the package to PCB. Pins must be soldered to PCB landing pads. The PCB landing pads are solder mask defined pads; this pin is not internally connected and is recommended to be connected to high voltage input (HVIN) to prevent charge build up; however this pin can also be left open.
PAD BP5H 74 P The BP5H pad provides a low electrical resistance path for the high side regulator, BP5H; PAD BP5H is internally connected to the BP5H pins (58-59).
PAD BP5L 69 P The BP5L pad provides a low electrical resistance path for the high side regulator, BP5L; PAD BP5L is internally connected to the BP5L pins 26-27.
PAD_GND 67, 68, 70 — Power GND pad utilized as the high current path, connected to the high-side GaN FET drain terminal for low-side driver signal return. PAD_GND pin 70 is internally connected to the low side FET source terminal and is to be used as the primary heat extraction path for the low side switch.
PAD HVIN 73 — Power HVIN pad utilized as the high current path, connected to the high-side GaN FET source terminal for thermal heat extraction. PAD HVIN is internally connected to HVIN pins 45-50, 52-56.
PAD SW_HS 65, 66, 72 — Power SW_HS pad utilized as the high current path, connected to the high-side GaN FET drain terminal. Also internally connected to pins SW_HS 9-10, 44-45, and 60-64. The TPS7H6101-SP has two electrically isolated GaN FETs and drivers; to form a half-bridge configuration, connect to SW_LS pad and pins.
PAD SW_LS 71 — Power SW_LS pad utilized as the high current path, connected to the low-side GaN FET source terminal. Internally connected to pins SW_LS(41-42). The TPS7H6101-SP has two electrically isolated GaN FETs and drivers; to form a half-bridge, connect to SW_HS pad and pins.
PGOOD 17 O Power good pin. Asserts low when any of the low-side internal linear regulators or VIN goes into undervoltage lockout. Requires a 10kΩ pull-up resistor to BP5L.
PWM_LI 19 I PWM input or low-side driver control input. In PWM mode this is used as the PWM input to the gate driver. In independent input mode (IIM) this serves as the control input for the low-side driver.
SW_HS 4–10, 44–45, 60–64 P High side driver signal return. SW_HS is internally connected to PAD SW_HS (65, 66 & 72). Pins 4-10 and pins 60-64 are not directly part of the high current path; pins 44-45 are in the high current path.
SW_LS 41–42 P Internally connected to PAD SW_LS and the low-side GaN FETs drain terminal; connect to SW_LS on the PCB; these pins are part of the high current path.
VIN 13 I Gate driver input voltage supply. Input voltage range is from 10V to 14V. This pin serves as the input to the low-side linear regulators and the internal bootstrap switch. For bootstrap charging directly from the input voltage, VIN also serves as the bootstrap diode anode connection point.
(1) I = Input, O = Output, G = Ground, P = Power, NC = No Connect, — = Other