SNOSDG7 May   2025 TPS7H6101-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Measurement
    2. 7.2 Deadtime Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gate Drive Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging Methods
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  PWM_LI and EN_HI
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode
      3. 9.2.3 Application Results
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

6.6 Switching Characteristics

Over ambient temperature operating range TA = -55°C to 125°C, VIN = 10V to 14V, HVIN = VSW_LS = 5V, VSW_HS = GND = 0V, IDS(HS) = IDS(LS) = 1mA (unless otherwise noted).
PARAMETER Test Conditions MIN TYP MAX UNIT
GATE DRIVE TIMING
tp(off)(ls) Low side turn-off propagation delay(1) From VPWM_LI = VIR to VLSG = 2.5V 
ID = 400mA
Mode = PWM
 		 41 51 ns
From VPWM_LI = VIF to VLSG = 2.5V 
ID = 400mA
Mode = IIM 
 		 33 42
tp(on)(ls) Low side turn-on gate drive propagation delay(1) From VPWM_LI = VIR to VLSG = 2.5V 
ID = 400mA
Mode = IIM
 		 33 42 ns
tp(off)(hs) High side turn-off propagation delay(1) From VPWM_LI = VIF to VHSG = 2.5V 
ID = 400mA  
Mode = PWM
 		 35 50 ns
From VEN_HI = VIF to VHSG = 2.5V 
ID = 400mA  
Mode = IIM 
 		 35 45
tp(on)(hs) High side turn-on propagation delay(1) From VEN_HI = VIR to VHSG = 2.5V 
ID = 400mA
Mode = IIM
 		 35 50 ns
td(on)(ls) Low side turn-on delay(1) From VPWM_LI = VIF to VDS(ls) = 4V 
ID = 400mA
Mode = PWM
 		 45 60 ns
From VPWM_LI = VIR to VDS(ls) = 4V 
ID = 400mA
Mode = IIM
 		 45 60
td(off)(ls) Low side turn-off delay(1) From VPWM_LI = VIR to VDS(ls) = 1V 
ID = 400mA
Mode = PWM
 		 51 79 ns
From VPWM_LI = VIF to VDS(ls) = 1V 
ID = 400mA
Mode = IIM 
 		 45 60
td(on)(hs) High side turn-on delay(1) From VPWM_LI = VIR to VDS(hs) = 1V 
ID = 400mA		 Mode = PWM 39 65 ns
From VEN_HI = VIR to VDS(hs) = 1V 
ID = 400mA		 Mode = IIM 39 65
td(off)(hs) High side turn-off delay(1) From VPWM_LI = VIF to VDS(hs) = 4V 
ID = 400mA		 Mode = PWM 45 65 ns
From VEN_HI = VIF to VDS(hs) = 4V 
ID = 400mA		 Mode = IIM 45 65
tMON Delay matching low side on and high side off(2) Mode = IIM 5 8 ns
tMOFF Delay matching low side off and high side on(2) MODE = IIM 5 8 ns
tPW(IIM) Minimum input pulse width (turn-on) MODE = IIM 5 8 ns
tPW(IIM)(OFF) Minimum input pulse width (turn-off) MODE = IIM 12 16 ns
tPW(PWM) Minimum required input pulse width for targeted dead time  MODE = PWM, RHL = 57.6kΩ, RLH = 35.7kΩ, DT reduction ≤ 0.5ns 12 ns
tPW(PWM) Minimum required input pulse width for targeted dead time MODE = PWM, RHL = 57.6kΩ, RLH = 35.7kΩ, DT reduction ≤ 3ns 30 ns
GAN FET
COSS(ls) Output capacitance - low side f = 1MHz
VSW_LS = 100V
VPWM_LI = 0V		 250 pF
COSS(hs) Output capacitance - high side f = 1MHz
VHVIN = 100V
VEN_HI = 0V		 250 pF
(1) Refer to Timing Measurement section for measurement configuration and waveform diagrams.
(2) Specification limits for this parameter are respresented as an absolute value.