SNOSDG7 May   2025 TPS7H6101-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Measurement
    2. 7.2 Deadtime Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gate Drive Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging Methods
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  PWM_LI and EN_HI
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode
      3. 9.2.3 Application Results
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

8.3.6 Dead Time

When operating in PWM mode, resistors to GND are required on both DLH and DHL to program the dead time. The DHL resistor sets the dead time between high-side gate (VHSG) turn-off to low-side gate (VLSG) output turn-on. Likewise, the resistor on DLH sets the dead-time between low-side gate (VHSG) turn-off to high-side (VLSG) turn-on. The resistor can be used to set the dead time from a minimum value of roughly 0.8ns up to 100ns. The resistor must be populated on both pins to operate the device in this mode. Refer to Figure 7-7 diagram.

The dead time values selected are critical as these directly impact that losses that occur in the converter during these periods. The dead time is carefully chosen to avoid cross-conduction between the high-side FET and low-side FET, while also minimizing the third-quadrant conduction time for the GaN FETs. TDLH and TDHL have been selected to minimize third quadrant time and avoid cross conduction events.

Equation 8 and Equation 9 can be used to obtain typical deadtime resistor values with the nearest E192 resistor value selected below.

RDHL:

Equation 8. R H L = 1.246 × T D H L + 5.13 = 1.246 × 42.5 n s + 5.13 = 58.05 k Ω

A value of 57.6kΩ is selected for RHL.

RDLH:

Equation 9. R L H = 1.046 × T D L H - 1.355 = 1.064 × 35 n s - 1.355 = 35.3 k Ω

A resistor value of 35.7kΩ was used for RLH.