SNOSDG7 May   2025 TPS7H6101-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Measurement
    2. 7.2 Deadtime Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gate Drive Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging Methods
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  PWM_LI and EN_HI
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode
      3. 9.2.3 Application Results
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

7.1 Timing Measurement

Figure 7-1 shows the circuit configuration used to measure the timing characteristics when in PWM Mode; when in PWM Mode, the FETs are configured in a "dual low-side" topology with independent test supplies. Figure 7-2 and Figure 7-3 show the measurement waveforms for propagation, turn-on and turn-off delays when configured in PWM Mode.

TPS7H6101-SEP Timing Measurement: PWM Mode Figure 7-1 Timing Measurement: PWM Mode
TPS7H6101-SEP Low Side Timing Measurement Waveform: PWM Mode Figure 7-2 Low Side Timing Measurement Waveform: PWM Mode
TPS7H6101-SEP High Side Timing Measurement Waveform: PWM Mode Figure 7-3 High Side Timing Measurement Waveform: PWM Mode

Figure 7-4shows the circuit configuration used to measure the timing characteristics when in Independent Input Mode (IIM); when in IIM Mode, the FETs are configured in a "dual low-side" topology with independent test supplies. Figure 7-5 and Figure 7-6 show the measurement waveforms for propagation, turn-on and turn-off delays when configured in IIM.

TPS7H6101-SEP Timing Measurement: IIM Figure 7-4 Timing Measurement: IIM
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TPS7H6101-SEP Low Side Timing Measurement Waveform: IIM Figure 7-5 Low Side Timing Measurement Waveform: IIM
TPS7H6101-SEP High Side Timing Measurement Waveform: IIM Figure 7-6 High Side Timing Measurement Waveform: IIM