SNOSDG7 May   2025 TPS7H6101-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Measurement
    2. 7.2 Deadtime Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Gate Drive Input Voltage
      2. 8.3.2  Linear Regulator Operation
      3. 8.3.3  Bootstrap Operation
        1. 8.3.3.1 Bootstrap Charging Methods
        2. 8.3.3.2 Bootstrap Capacitor
        3. 8.3.3.3 Bootstrap Diode
        4. 8.3.3.4 Bootstrap Resistor
      4. 8.3.4  High-Side Driver Startup
      5. 8.3.5  PWM_LI and EN_HI
      6. 8.3.6  Dead Time
      7. 8.3.7  Input Interlock Protection
      8. 8.3.8  Undervoltage Lockout and Power Good (PGOOD)
      9. 8.3.9  Negative SW Voltage Transients
      10. 8.3.10 Level Shifter
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bootstrap and Bypass Capacitor
        2. 9.2.2.2 Bootstrap Diode
      3. 9.2.3 Application Results
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

8.4 Device Functional Modes

The mode of operation for the TPS7H6101 is determined by the state of the DHL and DLH pins. The configuration of these pins cannot be changed during device operation. There are two different operational modes: PWM and independent input mode. In PWM mode, the EN_HI pin is used to enable the device and a single PWM input signal is required on PWM_LI and the internal gate driver generates the complementary output signals for the low side and high side. Since the primary application of this mode is a synchronous buck converter, the high side switch generates the main output and low side switch performs the synchronous rectification. Resistors are connected from DHL to GND and DLH to GND to program the dead time between the high-side and low-side outputs. For acceptable resistor values to use in PWM mode, refer to the Dead Time detailed description section.

In independent input mode (IIM), separate PWM input signals are required on PWM_LI and EN_HI. The corresponding outputs of the TPS7H6101 are driven directly from these inputs. In IIM with interlock disabled, DLH is tied to BP5L and DHL has a resistor connected to GND. For operation in IIM with interlock enabled, connect a resistor between DLH and GND while connecting DHL to BP5L. For both operating mode options in IIM, resistors used must be valued between 100kΩ and 220kΩ.

Table 8-1 shows the configuration for each operating mode. Note that these are the only valid operating modes for the driver, and the connections for DLH and DHL must adhere to one of these configurations for proper operation.

Table 8-1 TPS7H6101 Operating Mode Selection
Operating Mode DLH DHL
PWM Resistor to GND Resistor to GND
Independent input mode - input interlock disabled BP5L Resistor to GND (100kΩ to 220kΩ)
Independent input mode - input interlock enabled Resistor to GND (100kΩ to 220kΩ) BP5L

TPS7H6101-SEP Truth Table shows the truth table for each functional mode of the TPS7H6101-SP.

Table 8-2 TPS7H6101-SEP Truth Table
Inputs PWM Mode IIM - Interlock Disabled IIM - Interlock Enabled
EN_HI PWM_LI HS Gate LS Gate HS Gate LS Gate HS Gate LS Gate
0 0 0 0 0 0 0 0
0 1 0 0 0 1 0 1
1 0 0 1 1 0 1 0
1 1 1 0 1 1 0 0