GaN devices have very low output capacitance and
switch quickly with a high dv/dt, yielding very low switching losses. To preserve the
low switching losses, minimize the number of additional capacitances added to the output
node. Follow the below guidelines to minimize the PCB capacitance at the switch node:
- Minimize overlap between the switch-node plane
and other power and ground planes.
- Make the GND return path under the high-side
device thinner while still maintaining a low-inductance path.
- Choose high-side isolator ICs and bootstrap
diodes with low capacitance.
- Place the power inductor as close to the GaN
device as possible.
- Construct the power inductors with a single-layer
winding to minimize intrawinding capacitance.
- If a single-layer inductor is not possible,
consider placing a small inductor between the primary inductor and the GaN device to
effectively shield the GaN device from the additional capacitance.
- If using a back-side heat-sink, use the least
amount of area of the switch-node copper coverage on the bottom copper layer to improve
the thermal dissipation.