SNOSDJ7A February   2025  – December 2025 LMG3650R025

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Switching Parameters
      1. 6.1.1 Turn-On Times
      2. 6.1.2 Turn-Off Times
      3. 6.1.3 Drain-Source Turn-On and Turn-off Slew Rate
      4. 6.1.4 Zero-Voltage Detection Times (LMG3656R025 only)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 LMG3650R025 Functional Block Diagram
      2. 7.2.2 LMG3651R025 Functional Block Diagram
      3. 7.2.3 LMG3656R025 Functional Block Diagram
      4. 7.2.4 LMG3657R025 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Drive Strength Adjustment
      2. 7.3.2 GaN Power FET Switching Capability
      3. 7.3.3 VDD Supply
      4. 7.3.4 Overcurrent and Short-Circuit Protection
      5. 7.3.5 Overtemperature Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Fault Reporting
      8. 7.3.8 Auxiliary LDO (LMG3651R025 Only)
      9. 7.3.9 Zero-Voltage Detection (ZVD) (LMG3656R025 Only)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Slew Rate Selection
        2. 8.2.1.2 Signal Level-Shifting
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Using an Isolated Power Supply
      2. 8.3.2 Using a Bootstrap Diode
        1. 8.3.2.1 Diode Selection
        2. 8.3.2.2 Managing the Bootstrap Voltage
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Reliability
        2. 8.4.1.2 Power-Loop Inductance
        3. 8.4.1.3 Signal-Ground Connection
        4. 8.4.1.4 Bypass Capacitors
        5. 8.4.1.5 Switch-Node Capacitance
        6. 8.4.1.6 Signal Integrity
        7. 8.4.1.7 High-Voltage Spacing
        8. 8.4.1.8 Thermal Recommendations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information
    3.     70

5.6 Switching Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND/SRC; –40℃ ≤ TJ ≤ 150℃; VDD = 12V; FLT/RDRV resistances RDRVon & RDRVoff are open
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING TIMES
td(on) Turn-on delay time From VIN > VIN,IT+ to VDS < 320V, VBUS = 400V, LHB current = 0A, 80V/ns 45 55 ns
Turn-on current rise time + delay time From VIN > VIN,IT+ to VDS < 320V, VBUS = 400V, LHB current = 10A, 80V/ns 45 60 ns
tvf(on) Turn-on voltage falling time From VDS < 320V to VDS < 80V, VBUS = 400V, LHB current = 10A, 80V/ns 1 3.5 6 ns
Turn-on slew rate dv/dt when VDS = 200V, VBUS = 400V, LHB current = 10A, 80V/ns 60 80 100 V/ns
Pulse width distortion slew-rate setting at 80V/ns, IDS = 31A, Measure difference between IN pulse width & VSW pulse width 9 20 ns
Minimum input pulse changing the output L-H-L slew-rate setting at 80V/ns such that SW crosses 200V 50 ns
td(off) Turn-off delay time at full speed From VIN < VIN,IT- to VDS > = 80V. VBUS = 400V, IL  = 36A, fastest or full turn-off speed. 18 30 60 ns
tvr(off) Turn-off voltage rise time at full speed From VDS > = 80V to VDS > = 320V. VBUS = 400V, IL  = 36A, fastest or full turn-off speed. 3 5.5 7 ns
STARTUP TIMES
TDRV_START Driver startup delay From Driver supply crossing UVLO to switch turning on if IN is high.  56 70 µs
FAULT TIMES
toff(OC) Overcurrent fault FET turn-off time, FET on before overcurrent From ID > = IT(OC)  to Vds> 10V, di/dt = 100A/µs, in the fastest turn-off speed 340 480 ns
toff(OC_ON) Overcurrent  total on time, turn-on into overcurrent. From Vds < = 10V to Vds > = 10V, turning on at 110% of OC level, at 80V/ns turn-on slew rate and fastest turn-off speed. 420 580 ns
toff_cur(SC_ON) SC on time measured through drain current LS Vds > 10V, measured from LS Ids > 50A to Ids < 50A, at 80V/ns turn-on slew rate in a half-bridge configuration. 100 215 500 ns
toff_cur(SC) SC response time with source current measurement From LS Vds>9V to LS Ids<50A, at 80V/ns turn-on slew rate in a half-bridge configuration. . 155 350 ns
Latched-Fault reset time Time required to hold gate driver input low to clear latched-fault 300 380 450 µs
ZERO-VOLTAGE DETECTION AND ZERO-CURRENT DETECTION  TIMES
ZCD delay Current crossing zero (low to high) to ZCD output pulse di/dt = 0.03A/ns 15 40 75 ns
tDL_ZVD ZVD delay IN rising to ZVD output pulse. 80V/ns turn-on speed. 35 50 58 ns
tWD_ZVD ZVD pulse width Vbus = 10V, IL = 5A, measure ZVD pulse width 90 120 170 ns
t3rd_zvd 3rd quadrant conduction time when the ZVD pulse starts to appear Vbus = 10V, IL = 5A, measure the 3rd quadrant conduction time when the ZVD pulse starts to appear, fet turn on (80V/ns). 20 30 ns