SNOSDJ7A February   2025  – December 2025 LMG3650R025

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Switching Parameters
      1. 6.1.1 Turn-On Times
      2. 6.1.2 Turn-Off Times
      3. 6.1.3 Drain-Source Turn-On and Turn-off Slew Rate
      4. 6.1.4 Zero-Voltage Detection Times (LMG3656R025 only)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 LMG3650R025 Functional Block Diagram
      2. 7.2.2 LMG3651R025 Functional Block Diagram
      3. 7.2.3 LMG3656R025 Functional Block Diagram
      4. 7.2.4 LMG3657R025 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Drive Strength Adjustment
      2. 7.3.2 GaN Power FET Switching Capability
      3. 7.3.3 VDD Supply
      4. 7.3.4 Overcurrent and Short-Circuit Protection
      5. 7.3.5 Overtemperature Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Fault Reporting
      8. 7.3.8 Auxiliary LDO (LMG3651R025 Only)
      9. 7.3.9 Zero-Voltage Detection (ZVD) (LMG3656R025 Only)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Slew Rate Selection
        2. 8.2.1.2 Signal Level-Shifting
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Using an Isolated Power Supply
      2. 8.3.2 Using a Bootstrap Diode
        1. 8.3.2.1 Diode Selection
        2. 8.3.2.2 Managing the Bootstrap Voltage
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Reliability
        2. 8.4.1.2 Power-Loop Inductance
        3. 8.4.1.3 Signal-Ground Connection
        4. 8.4.1.4 Bypass Capacitors
        5. 8.4.1.5 Switch-Node Capacitance
        6. 8.4.1.6 Signal Integrity
        7. 8.4.1.7 High-Voltage Spacing
        8. 8.4.1.8 Thermal Recommendations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information
    3.     70

7.3.1 Drive Strength Adjustment

The LMG365xR025 allows users to adjust the drive strength of the device and obtain a desired slew rate, which provides flexibility when optimizing switching losses and minimizing EMI. Independently control the typical value of turn-on slew rate and the maximum value of turn-off slew rate by connecting the resistors and capacitor as shown in the Drive Strength Adjustment Circuit. The resistance and capacitance on FLT/RDRV pin is sensed once at power-up. To do so, the device forces a step-function from 0V to 1.2V on the external RDRVon-RDRVoff-CDRVoff network and measures the resulting current waveform. The DC measurement (Iup) determines the turn-on slew rate setting, which is programmed by the resistance RDRVon. The AC measurement dependent on RDRVon-RDRVoff-CDRVoff determines the turn-off slew rate setting, which is dependent on the magnitude of the drain-to-source current charging the output capacitance but can be limited to a maximum value programmed by the resistance RDRVoff and capacitance CDRVoff, connected in parallel to RDRVon.

Equation 1. I up = 1 . 2 RDRV on A

Turn-On Slew Rate Control Table and Turn-Off Slew Rate Control Table show the recommended typical resistances and capacitance programming values at each slew rate setting. The RDRVon values listed in the table assume no parasitic resistance on the FLT/RDRV pin. However, in real applications, this pin is often connected to an isolator input for fault monitoring. The internal configuration of the isolator can include either a pull-up or pull-down resistor, causing a mismatch between the measured and programmed slew rates—since both fault monitoring and drive strength adjustment share the same pin FLT/RDRV. An internal pull-up is not preferred, as the voltage at the FLT/RDRV pin is altered through a voltage divider with the supply of the isolator, Rpull-up, and RDRVon, thus reducing control over Iup. Using an isolator with an internal pull-down resistor is recommended, as it forms a parallel path with RDRVon, then Iup is determined by (Rpull-down || RDRVon). To match the programmed turn-on slew rate settings, adjust RDRVon so that new Iup remains consistent with the programmed value.

Equation 2. I up = 1 . 2 ( Rpull - down ∥ RDRV on ) A

The slew rate settings are determined one time at power up, then the FLT/RDRV pin is used as a push-pull 5V digital output for fault monitoring, as described in Fault Reporting. If RDRVoff and CDRVoff are not used, the device turns-off at full-speed and the turn-off slew rate is strictly determined by the Coss and the load current. If RDRVon is not used, the device defaults to the 80V/ns slew rate setting. Using slower turn-on settings results in higher Eon losses, and slower turn-off settings results in higher Eoff losses.

LMG3650R025 LMG3651R025 LMG3656R025 LMG3657R025 Drive Strength Adjustment Circuit Figure 7-1 Drive Strength Adjustment Circuit
Table 7-1 Recommended Typical Programming Resistance (kΩ) for Adjusting Turn-on Slew Rates
TYPICAL TURN-ON SLEW RATE (V/ns) RDRVon(kΩ)(1)
10 29.4
20 35.7
40 43.2
60 53.6
70 69.8
80 > 400(2)
(1) Fully dependent on the magnitude of the drain-to-source current charging the output capacitance.
(2) Open-circuit connection for programming resistances is acceptable.
Table 7-2 Recommended Typical Programming Resistance (kΩ) and Capacitance (pF) for Adjusting Turn-off Slew Rate Limits
MAXIMUM TURN-OFF SLEW RATE (V/ns) RDRVoff(kΩ)(1) CDRVoff(pF)(2)
10 2 1800
20 3.57 1000
40 7.68 470
Unlimited(1) High impedence High impedence
(1) ±1% tolerance on resistance values.
(2) ±10% tolerance on capacitance values.

For example, setting RDRVon = 53.6kΩ, RDRVoff = 3.57kΩ and CDRVoff = 1000pF results in turn-on slew rate of 60V/ns and turn-off slew rate is limited to a maximum of 20V/ns.

Note: Parasitic power loop inductance can influence the voltage slew rate reading from the VDS switching waveform. The inductance induces a drop on VDS in the current rising phase before voltage falling phase, if this drop is more than 20% of the VDC, the voltage slew rate reading can be influenced. Refer to Section 8.4.1.2 for the power loop design guideline and how to estimate the parasitic power loop inductance.