The power loop, comprising of the two devices in the half bridge and the high-voltage bus capacitance, undergoes high di/dt during switching events. By minimizing the inductance of the power loop, ringing and electromagnetic interference (EMI) can reduce, as well as a reduction in the voltage stress on the devices.

Place the power devices as close as possible to minimize the power-loop inductance. Position the decoupling capacitors in line with the two devices, close to either device. In Section 8.4.2, the decoupling capacitors are placed on the same layer as the devices. The return path (PGND in this case) is located on second layer in close proximity to the top layer. By using inner layer and not bottom layer, the vertical dimension of the loop reduces, thus minimizing inductance. A large number of vias near both the device terminal and bus capacitance carry the high-frequency switching current to the inner layer, while minimizing impedance.

Estimate the power loop inductance based on the ringing frequency f_ring of the drain-source voltage switching waveform based on the following equation:

In Equation 4, C_ring is equal to C_OSS at the bus voltage (refer to Output Capacitance vs Drain-Source Voltage for the typical value) plus the drain-source parasitic capacitance from the board and load inductor or transformer.

As the parasitic capacitance of load components is hard to characterize, TI recommends capturing the V_DS switching waveform without load components to estimate the power loop inductance. Typically, the power loop inductance of the Section 8.4.2 is approximately 2.5nH.