SNOSDJ7A February   2025  – December 2025 LMG3650R025

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Switching Parameters
      1. 6.1.1 Turn-On Times
      2. 6.1.2 Turn-Off Times
      3. 6.1.3 Drain-Source Turn-On and Turn-off Slew Rate
      4. 6.1.4 Zero-Voltage Detection Times (LMG3656R025 only)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 LMG3650R025 Functional Block Diagram
      2. 7.2.2 LMG3651R025 Functional Block Diagram
      3. 7.2.3 LMG3656R025 Functional Block Diagram
      4. 7.2.4 LMG3657R025 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Drive Strength Adjustment
      2. 7.3.2 GaN Power FET Switching Capability
      3. 7.3.3 VDD Supply
      4. 7.3.4 Overcurrent and Short-Circuit Protection
      5. 7.3.5 Overtemperature Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Fault Reporting
      8. 7.3.8 Auxiliary LDO (LMG3651R025 Only)
      9. 7.3.9 Zero-Voltage Detection (ZVD) (LMG3656R025 Only)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Slew Rate Selection
        2. 8.2.1.2 Signal Level-Shifting
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Using an Isolated Power Supply
      2. 8.3.2 Using a Bootstrap Diode
        1. 8.3.2.1 Diode Selection
        2. 8.3.2.2 Managing the Bootstrap Voltage
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Reliability
        2. 8.4.1.2 Power-Loop Inductance
        3. 8.4.1.3 Signal-Ground Connection
        4. 8.4.1.4 Bypass Capacitors
        5. 8.4.1.5 Switch-Node Capacitance
        6. 8.4.1.6 Signal Integrity
        7. 8.4.1.7 High-Voltage Spacing
        8. 8.4.1.8 Thermal Recommendations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     PACKAGE OPTION ADDENDUM
    2. 11.1 Tape and Reel Information
    3.     70

5.5 Electrical Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND/SRC; –40℃ ≤ TJ ≤ 150℃; VDD = 12V; FLT/RDRV resistances RDRVon & RDRVoff are open
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GAN POWER FET
RDS(on) Drain-source on resistance TJ = 25°C, IL = 16A 22 30 mΩ
TJ = 150°C, IL = 16A 44 mΩ
VSD Source-drain third-quadrant voltage TJ = 25°C, ISD = 0.1A 1.8 V
TJ = 150°C, ISD = 0.1A 1.6 V
TJ = 25°C, ISD = 20A 3.4 V
TJ = 150°C, ISD = 20A 4.8 V
IDSS Drain leakage current TJ = 25°C, VDS = 650V 7 µA
TJ = 150°C, VDS = 650V 10 µA
COSS Output capacitance VDS = 400V 200 pF
QOSS Output charge VDS = 0V to 400V 150 nC
EOSS Output capacitance stored energy 23 µJ
COSS(tr) Time related effective output capacitance 400 pF
COSS(er) Energy related effective output capacitance 280 pF
QRR Reverse recovery charge 0 nC
OVERCURRENT AND SHORT-CIRCUIT PROTECTIONS
IT(OC) Overcurrent fault - threshold current   TJ = -40℃  57 63 69 A
TJ = 25℃  50 55 60 A
TJ = 150℃  38 43 48.5 A
VT(Idsat) Saturation current detection - threshold voltage 8.5 9 9.6 V
OVERTEMPERATURE PROTECTION
TT+ Temperature fault - positive-going threshold temperature 190 °C
TT(hyst) Temperature fault - threshold temperature hysterisis 20 °C
IN
VIN,IT+ Positive-going input threshold voltage 1.6 2 2.45 V
VIN,IT- Negative-going input threshold voltage 0.6 0.9 1.3 V
VIN,IT(hyst) Input threshold voltage hysteresis 1 V
RPDN Pull-down input resistance 115 150 185 kΩ
FLT/RDRV
VOL Low-level output voltage Output sink 8mA 0.2 0.4 V
VOH High-level output voltage Output source 8mA 4.5 4.8 V
VDD
IVDD(ON) Quiescent current when FET is ON IN=1 1.2 16 mA
IVDD(OFF) Quiescent current when FET is OFF IN=0 0.8 1.1 mA
ICC_op Operation current at 140kHz fsw = 140kHz, Vbus = 0V, Soft-switched, 50% duty cycle. 4 5.6 mA
VVDD, T+ (UVLO) UVLO- positive-going threshold voltage 8.1 8.5 8.9 V
VVDD, T- (UVLO) UVLO- negative-going threshold voltage 7.6 8 8.4 V
VVDD, T (hyst) UVLO- threshold voltage hystresis 0.5 V