SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

2.5 Power Distribution Network

This section outlines the latest estimates of the AM26x transient current requirements on a per net basis. These values can change as more power modeling and characterization is performed.

These transient use-case values were used to constrain the PDN design of the AM26x EVMs (controlCards, LaunchPads, and controlSOM) by creating a set of minimum/maximum operating frequency and PDN impedance (Zmax) target limits. These limits were based on the magnitude and slew-rate of simulated transient current use-cases. The use-cases were used to estimate the PDN bandwidth needed to adequately decouple the resulting transient event. Additional z-parameter simulation of the EVM PDN was used to verify that the power plane design and decoupling placement and component values meet the defined limits. This is summarized in Figure 2-12.

AM26x PDN Requirements – Example Diagram Figure 2-12 AM26x PDN Requirements – Example Diagram
Table 2-12 AM26x Transient Current Model – Use-case Conditions
Transient Case Net Name Nominal Voltage (V) DC IR Budget (%) AC Ripple Budget (%) Idle Current (mA) Peak Current (mA) Idle to Peak Slew Rate (ns) Comment
VDDBASELINE1 VDD 1.2 2.5 2.5 0 2402 2.5 Baseline, simple transient model assuming 0 to peak transition in minimal 1 R5F clock cycle.
VDDXTAL_PLL1 VDD 1.2 2.5 2.5 42 875 10 XTAL to PLL turn-on transient
VDD WFI1 VDD 1.2 2.5 2.5 750 1117 12.5 4x RF5 WFI event transient
VDDS33BASELINE1 VDDS33 3.3 2.5 2.5 0 84 2.5 Baseline, simple transient model assuming 0 to peak transition in a single R5F clock cycle
VDDA33BASELINE1 VDDA33 3.3 2.5 2.5 0 34 2.5 Baseline, simple transient model assuming 0 to peak transition in a single R5F clock cycle
VDDS18LDOBASELINE1 VDDS18LDO 1.8 2.5 2.5 0 01 2.5 Baseline, simple transient model assuming 0 to peak transition in minimal 1 R5F clock cycle
VDDA18LDOBASELINE1 VDDA18LDO 1.8 2.5 2.5 0 66 2.5 Baseline, simple transient model assuming 0 to peak transition in minimal 1 R5F clock cycle
Table 2-13 AM26x Transient Current Model – Resulting PDN Requirements
Transient Case Net Name Fmax (MHz) Current Step(mA) PCB DC Tolerance(mV) PCB AC Tolerance(mV) PCB Target DC IR(mΩ) PCB Target AC Zmax(mΩ) Comment
VDD
BASELINE1		 VDD 200 2402 30 30 12 12 Baseline, simple transient model assuming 0 to peak transition in minimal 1 R5F clock cycle.
VDD
XTAL_PLL1		 VDD 50 833 30 30 36 36 XTAL to PLL turn-on transient.
VDD
WFI1		 VDD 40 367 30 30 82 82 4x RF5 WFI event transient.
VDDS33
BASELINE1		 VDDS33 200 84 83 83 982 982 Baseline, simple transient model assuming 0 to peak transition in minimal 1 R5F clock cycle.
VDDA33
BASELINE1		 VDDA33 200 34 83 83 2419 2419 Baseline, simple transient model assuming 0 to peak transition in minimal 1 R5F clock cycle.
VDDS18LDO
BASELINE1		 VDDS18LDO 200 1 45 45 45 45 Baseline, simple transient model assuming 0 to peak transition in minimal 1 R5F clock cycle.
VDDA18LDO
BASELINE1		 VDDA18LDO 200 66 45 45 682 682 Baseline, simple transient model assuming 0 to peak transition in minimal 1 R5F clock cycle.