SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

4 Resets

The AM26x MCUs have two hardware reset sources:

  • PORz: Power on reset (logic low enable) pin
    • Must be driven from the power-good circuits of the associated VDD 1.2V core and VDDS33 3.3V I/O regulators or PMIC reset signal
    • For a valid reset the PORz signal must transition from logic low to logic high only after the VDD 1.2V core and VDDS33 3.3V I/O regulators are stable at the nominal values. For power-on-reset timing requirements, see the device-specific data sheet.
  • WARMRSTn: Warm reset (logic low enable) input and reset status output pin
    • At power-on, the default configuration sets this pin as open-drain output, which outputs the reset status of the device.
    • When the device enters reset, this signal is driven logic low.
    • When the device is fully out of reset, this signal is driven logic high.

PORz

The PORz is intended to be kept at logic low at initial startup of the system. Once each regulator sourcing the AM26x power pins has been verified to be operating at nominal output voltage, then the PORz signal can be brought up to logic high. This action starts the MCU boot ROM execution, beginning with sampling of the SOP pins.

PORz - Discrete Power Tree Implementation

The AM263x LaunchPad implementation utilizes a single SN74LVC1G11 AND gate which takes the open-drain output power-good signals from the onboard DC-DC regulators and an optional push-button reset switch as inputs to the AND gate. A weak pull-down resistor is recommended on the PORz signal to keep the signal at logic low before system startup. PORz must be forced low if either VDD 1.2V or VDDS33 3.3V rail power goes below the nominal operating range.

Excerpt From AM263x Launchpad Schematic – PORz Generation Figure 4-1 Excerpt From AM263x Launchpad Schematic – PORz Generation

PORz - PMIC Based Power Design Implementation

For AM26x systems that utilize a PMIC-based power design, the PORz logic is slightly more complex. On the AM263Px controlCARD, the open-drain output power-good signal from the 1.2V regulator, the optional push-button reset switch, and the nRST signal from the PMIC are inputs to a SN74LVC1G11 AND gate. The output of the 3-input AND gate is connected to the input of a 2-input SN74LVC1G08 AND gate, with the other input being the output of a voltage divider of the system input voltage (5V) divided down to 0.88V. The output of the SN74LVC1G08 is connected to the AM26x PORz. The SN74LVC1G08 low-level input voltage is 0.8V, so the AND gate outputs a logic 0 if the input voltage drops below 0.8V, thus triggering a reset.

Excerpt from AM263Px controlCARD Schematic- PORz Generation Figure 4-2 Excerpt from AM263Px controlCARD Schematic- PORz Generation

For AM261x system designs that use a single PMIC power design, such as TPS650360, the PORz generation is sourced from the PMIC nRSTOUT signal ANDed with a reset pushbutton. This is a simple and valid design that involves less redundancy and components.

Excerpt from AM261x LaunchPad Schematic - PORz Generation Figure 4-3 Excerpt from AM261x LaunchPad Schematic - PORz Generation

For a full description of the power-on and power-off reset sequencing requirements, see the device-specific AM26x data sheet.

WARMRSTn

The WARMRSTn pin is a multipurpose software reset input and hardware reset status pin. In the power-on-default configuration, this pin is configured as an open-drain output and requires an external pull-up resistor to VDDS33 3.3V I/O voltage rail. In this mode, WARMRSTn can be used as an MCU reset indicator and can be used to drive reset input for attached peripheral IC such as Ethernet PHY and memories.

Excerpt From AM263x Control Card Schematic – PORz and WARMRSTn Pinout Figure 4-4 Excerpt From AM263x Control Card Schematic – PORz and WARMRSTn Pinout

WARMRSTn can also be configured as a software reset. Additional software reset sources are available on the AM26x devices. For more information on reset functionality, see the Reset chapter in the device specific AM26x Technical Reference Manual.

Because of the default open-drain configuration of this pin, if both the reset status output mode and the software reset input mode is needed in a design, open-drain buffers are recommended to drive the optional reset input status. In the case of the AM263x Control Card, a SN74LVC1G07 open-drain buffer is used to optionally drive the push-button WARMRSTn without conflicting with the reset status output which is used to reset the Ethernet PHY onboard during initial board power-on.

Excerpt From AM263x Control Card Schematic – WARMRSTn Push-Button Open-Drain Driver Figure 4-5 Excerpt From AM263x Control Card Schematic – WARMRSTn Push-Button Open-Drain Driver