SPRABJ8 User guide

SPRABJ8D September 2022 – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

1
Abstract
Trademarks
1 Introduction
2 Power
1. 2.1 Discrete DC-DC Power Solution
2. 2.2 Integrated PMIC Power Solution
3. 2.3 Power Decoupling and Filtering
  1. 2.3.1 ADC/DAC Voltage Reference Decoupling
4. 2.4 Estimated Power Consumption
5. 2.5 Power Distribution Network
  1. 2.5.1 Simulations
    1. 2.5.1.1 Core Digital Power 1.2V
    2. 2.5.1.2 Digital and Analog I/O Power 3.3V
6. 2.6 eFuse Power
3 Clocking
1. 3.1 Crystal and Oscillator Input Options
2. 3.2 Output Clock Generation
3. 3.3 Crystal Selection and Shunt Capacitance
4. 3.4 Crystal Placement and Routing
4 Resets
5 Bootstrapping
1. 5.1 SOP Signal Implementation
6 OSPI and QSPI Memory Implementation
1. 6.1 ROM OSPI and QSPI Boot Requirements
2. 6.2 Additional OSPI and QSPI References
7 Debug Interfaces
1. 7.1 JTAG Emulators and Trace
2. 7.2 UART
8 USB
1. 8.1 USB Device Mode
2. 8.2 USB Host Mode
9 Multiplexed Peripherals
10Digital Peripherals
1. 10.1 General Digital Peripheral Routing Guidelines
2. 10.2 Trace Length Matching
11Analog Peripherals
1. 11.1 General Analog Peripheral Routing Guidelines
  1. 11.1.1 Resolver ADC Routing Guidelines
12Layer Stackup
1. 12.1 Key Stackup Features
13Vias
14BGA Power Fan-Out and Decoupling Placement
1. 14.1 Ground Return
  1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
  2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
2. 14.2 1.2V Core Digital Power
  1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
  2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
3. 14.3 3.3V Digital and Analog Power
  1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
  2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
4. 14.4 1.8V Digital and Analog Power
  1. 14.4.1 1.8V Key Layout Considerations - ZCZ
  2. 14.4.2 1.8V Key Layout Considerations - ZFG
15Summary
16References
17Revision History

5.1 SOP Signal Implementation

Each SOP bootmode selection signal is multiplexed with a subset of OSPI/QSPI and SPI peripheral functional mode signals. For all signal descriptions, see the Signal Description tables in the device-specific AM26x Data Sheet.Data Sheet. The SOP signal descriptions are excerpted in Figure 5-1. The SoC pin number differs depending on device package type.

Table 5-1 SOP and Functional Mode Signal Mapping

SOP Mode Signal	Primary Pinmux Signal	AM26x ZCZ Pin	AM261x ZFG Pin	AM261x ZNC Pin	AM261x ZEJ Pin
SOP[0]	OSPI0/QSPI0_D0	N1	R2	N2	M2
SOP[1]	OSPI0/QSPI_D1	N4	R1	N1	N1
SOP[2]	SPI0_CLK	A11	A13	A12	A12
SOP[3]	SPI0_D0	C10	B12	B12	A10

Because of this SOP/functional-mode multiplexing additional care must be taken in schematic and layout to make sure that the SOP mode selection resistors, jumpers or switch paths are routed in such a way that the SOP mode branches do not present inductive PCB trace stubs to the functional mode signal paths. Failing to take care of this can result in non-functional OSPI/QSPI or SPI.

Figure 5-1 Excerpt From AM263x Launchpad Schematic – SOP[3:0] Functional and SOP Paths

In the AM263x and AM263Px EVM designs, this SOP mode isolation is accomplished by including a 10KΩ resistor in the SOP signal path. The resistor is placed such that one pad is as close to the AM263x BGA pad and in-line with the functional mode path. This creates a layout where the additional stub length necessary to breakout the SOP path results in minimal impact to the functional mode operation of the signals, as shown in Figure 5-2 and Figure 5-3.

Figure 5-2 Excerpt From AM263x Launchpad Layout – All SOP[3:0] Functional and SOP Paths

Figure 5-3 Excerpt From AM263x Launchpad Layout – Highlighting SOP0/QSPI_D0 Path and SOP Isolation Resistor

AM261x ZFG, ZEJ, ZNC Package SOP Isolation

On the AM261x ZFG/ZEJ/ZNC package devices, additional isolation is required to prevent driving the SOP pins before boot is complete, as the functional mode signals shared with the SOP nets are capable of driving the SOP[3:0] states strong enough to disrupt the boot mode setting. This is accomplished on the AM261x LaunchPad by implementing a mux with SOP pin functional mode signals as the inputs, and the nets shared with the SOP signals as the outputs. The Output Enable pin on the mux is controlled by an RC delay circuit driven by the device PORz signal. The RC delay circuit holds the mux enable signal low long enough for the SOP[3:0] pins to be driven and the device boot mode to be latched, thus preventing any voltage applied to the functional mode pins from driving the SOP nets. This scheme is detailed in the following figures:

Figure 5-4 LP-AM261 SOP Isolation Resistors

Figure 5-5 LP-AM261 SOP Isolation Mux

Figure 5-6 LP-AM261 PORz SOP Driver RC Delay

Figure 5-7 LP-AM261 SOP State Driver

Figure 5-8 LP-AM261 SOP Isolation Mux Output Enable Generation

Figure 5-9 LP-AM261 SOP Isolation - Layout

The LP-AM261 implementation is likely more complex than necessary for a typical AM261x system due to the wide range of functions the EVM is required to support. For a simpler implementation, tying the delayed PORz signal to the isolation mux enable is sufficient. The key requirement is that there must be sufficient time for the SOP signals to latch the boot mode before any applied voltage is exposed to the shared functional signals.