SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

6.1.1 AM263x QSPI Boot Pin Requirements

The following pins are configured in the device boot ROM to enable boot from the QSPI flash device. These pins must be used in the connection between the AM263x MCU and QSPI flash.

Table 6-4 AM263x QSPI Pins Configured in Boot ROM
Package Name Function Name GPIO # PinMux Mode #
QSPI0_CSn0 QSPI0_CSn0 0 0
QSPI0_CLK0 QSPI0_CLK0 2 0
QSPI0_D0 QSPI0_D0 3 0
QSPI0_D1 QSPI0_D1 4 0
QSPI0_D2 QSPI0_D2 5 0
QSPI0_D3 QSPI0_D3 6 0
QSPI_CLKLB QSPI_CLKLB 145 0

Reset

When using a QSPI\SPI flash device greater than 128Mb, a flash device package with a RESET signal must be used. This is due to the ROM only using a 3 byte addressing mode (address is 24 bits). To address the full memory address range, software typically switches to 4 byte addressing mode. If a reset to the processor occurs (for example, due to a warm reset), then the ROM executes expecting 3 byte addressing mode, but the flash is left in 4 byte addressing mode. For the flash device to return to 3-byte addressing mode, the flash device must be reset using this signal. This typically can be achieved by using the RESET signal on the flash memory device. ROM code does not issue a software reset command.

For more information, refer to the QSPI Boot in the Initialization section of the AM263x Technical Reference Manual.