SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

6.1.3 AM261x OSPI and QSPI Boot Pin Requirements

The following pins are configured in the device boot ROM to enable boot from the OSPI (or QSPI) flash device. These pins must be used in the connection between the AM261x MCU and flash device.

Table 6-7 AM261x ZCZ Package OSPI Pins Configured in Boot ROM
Package Name Function Name GPIO # PinMux Mode #
OSPI0_CSn0 OSPI0_CSn0 0 0
OSPI0_CLK0 OSPI0_CLK0 2 0
OSPI0_D0 OSPI0_D0 3 0
OSPI0_D1 OSPI0_D1 4 0
OSPI0_D2 OSPI0_D2 5 0
OSPI0_D3 OSPI0_D3 6 0
MCAN0_RX OSPI0_D4 7 2
MCAN0_TX OSPI0_D5 8 2
MCAN1_RX OSPI0_D6 9 2
MCAN1_TX OSPI0_D7 10 2
Table 6-8 AM261x ZFG, ZEJ, ZNC Package OSPI Pins Configured in Boot ROM
Package Name Function Name GPIO # PinMux Mode #
EPWM9_B OSPI0_CSn0 62 6
MCAN1_TX OSPI0_CLK0 10 5
OSPI0_CLK OSPI0_D0 2 4
PR1_PRU0_GPIO9 OSPI0_D1 70 6
MCAN0_RX OSPI0_D2 7 5
PR1_PRU0_GPIO2 OSPI0_D3 69 2
UART1_TXD OSPI0_D4 76 2
PR1_PRU0_GPIO0 OSPI0_D5 67 2
MCAN0_TX OSPI0_D6 8 2
PR1_PRU0_GPIO1 OSPI0_D7 68 2
Note: For AM261x devices in OSPI boot mode, the Boot ROM configures GPIO61 as the OSPI0_RESET_OUT0 signal and drives the pin low to reset an external OSPI device during this boot mode. However, due to a reset signal management issue in the OSPI controller, this pin does not de-assert after an external OSPI flash device resets, thus holding any external flash device in reset and causing the boot to fail. Refer to the AM261x Errata for more details. Workarounds are detailed in the following sections.

OSPI Reset Implementation 1: PORz, WARMRESETn

Booting from an OSPI flash requires the flash to be reset before loading data to the AM261x device. Directly connecting PORz or WARMRESETn from the AM261x MCU to the flash device makes sure that the flash is reset upon system power-on, as PORz, WARMRESETn are LOW during boot and drive HIGH once power supplies are stable. Make sure that PORz or WARMRESETn are at the correct IO voltage level as the flash device.

Resetting OSPI Flash Using PORz or WARMRESETn Figure 6-7 Resetting OSPI Flash Using PORz or WARMRESETn

OSPI Reset Implementation 2: Other GPIO with OSPI0_RESET_OUT0 PinMux (Suggested)

This implementation is recommended because there are both hardware and software reset options, and does not require an additional buffer. Any of the AM261x GPIOs listed in Table 6-9 can be used post-boot as reset inputs to the OSPI flash reset logic, per the device data sheet pin mux. Make sure that the voltage levels of the reset logic inputs and output align with the flash device IO voltage. The suggested implementation is shown in Figure 6-8.

Resetting OSPI Flash Using OSPI0_RESET_OUT0 and PORz, WARMRESETn Figure 6-8 Resetting OSPI Flash Using OSPI0_RESET_OUT0 and PORz, WARMRESETn
Table 6-9 OSPI0_RESET_OUT0 Pin Options
GPIOx PinMux Mode #
GPIO18(1) 4
GPIO20 1
GPIO54 3
GPIO64(2) 2
GPIO66(1) 0
(1) ZCZ, ZFG, ZEJ packages only
(2) ZCZ, ZFG packages only

OSPI Reset Implementation 3: Buffered GPIO61

GPIO61 can still be used to reset the OSPI flash by software as OSPI0_RESET_OUT0. This signal must be connected to an AND gate with PORz, WARMRESETn as the other input to drive the reset input to the flash device. However, the GPIO61 signal must be buffered at boot to prevent the LOW signal from propagating to the OSPI reset logic. This can be done by configuring the buffer output enable pin with a pull-down resistor and driving the output enable using any GPIO on the AM261x device. Make sure that the voltage levels of the reset logic inputs and output align with the flash device IO voltage.

Resetting OSPI Flash using Buffered GPIO61 and PORz, WARMRESETn Figure 6-9 Resetting OSPI Flash using Buffered GPIO61 and PORz, WARMRESETn