SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. Resets
  8. Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

3.3V I/O Power Key Layout Considerations - ZCZ

The 3.3V power system on AM26x ZCZ devices are explored using the AM263x controlCARD EVM (TMDSCNCD263), from the 3.3V buck-converter (TPS62913RPUR, U30) through the board power planes and ending in at the BGA bulk and per pin decoupling capacitor array. A common buck-converter supplies power for all of the AM263x digital I/O, analog I/O and the rest of the controlCard 3.3V loads. This is common in most designs where all 3.3V digital level I/O share a common power supply. Additional filtering for the local AM263x 3.3V analog power net is done through the LC filter of ferrite-bead FL13 and associated capacitors. This is used to create a low-IR drop low-pass filter that attenuates the higher frequency switching harmonics of the TPS62913RPUR regulator.

  • Wide 15 mil traces need to be used for all power and ground return via fan-out.
  • 3.3V I/O power tends to be shared across multiple devices in the system, recommend routing with very wide power planes across the PCB to minimize IR drops to all components including AM263x, AM263Px, or AM261x.
  • A tightly coupled, adjacent ground return reference plane needs to be used for best transient performance and EMI coupling.
  • A wide power plane entry that covers the BGA 3.3V power pin areas needs to be used for minimal IR drop and best transient performance.
  • Larger packaged, lower-frequency, bulk capacitance needs to be placed adjacent to MCU BGA with vias directly to power plane paths.
  • Smaller packaged, higher-frequency decoupling capacitance needs to be placed directly on BGA fan-out vias with as small of a dog-bone to power and ground return vias as possible.
 AM263x controlCARD Excerpt –
                    3.3V Digital and Analog Power Planes on Layer 5 and Layer 6 Figure 14-12 AM263x controlCARD Excerpt – 3.3V Digital and Analog Power Planes on Layer 5 and Layer 6
 AM263x controlCARD Excerpt –
                    3.3V Digital I/O and Analog I/O BGA Pinout and Regulator Output Figure 14-13 AM263x controlCARD Excerpt – 3.3V Digital I/O and Analog I/O BGA Pinout and Regulator Output
 AM263x controlCARD Excerpt –
                    Common 3.3V Plane Transition Vias Figure 14-14 AM263x controlCARD Excerpt – Common 3.3V Plane Transition Vias
 AM263x controlCARD Excerpt –
                    3.3V Digital and Analog Planes Layer 6 Figure 14-15 AM263x controlCARD Excerpt – 3.3V Digital and Analog Planes Layer 6
 AM263x controlCARD Excerpt –
                    3.3V Digital and Analog Power Decoupling Mounting, Layer 10 Figure 14-16 AM263x controlCARD Excerpt – 3.3V Digital and Analog Power Decoupling Mounting, Layer 10