SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. 6 OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. 7 Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. 8 USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. 9 Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

8 USB

The AM261x family of microcontroller devices include an internal USB 2.0 PHY that supports USB Device Mode, USB Host Mode, and USB Dual-Role Mode operation. The internal USB 2.0 PHY is capable of high speed (HS, 480Mbps) and full speed (FS, 12Mbps) operation in both USB 2.0 Host and Device mode, and low speed (LS, 1.5Mbps) operation in host mode only.

The critical component of the internal USB PHY is the bidirectional differential data pins USB0DM (D-) and USB0DP (D+). The USB0_ID signal is an external net that interfaces with the USB receptacle, indicating which mode the USB2.0 PHY is operating in. On the AM261x EVMs, USB0_ID is set with a switch, allowing evaluation of the USB 2.0 PHY for both modes.

USB 2.0 Micro-AB Port Showing Critical Signals - LP-AM261 Figure 8-1 USB 2.0 Micro-AB Port Showing Critical Signals - LP-AM261

The following design rules and recommendations need to be followed when routing the USB differential pair for best results:

  • Route the USB differential pair on the top layer with trace width and differential spacing tuned to the PCB stack-up for 90Ω differential impedance.
    • This can be difficult to implement a trace geometry that achieves both 90Ω differential impedance and 45Ω single-ended impedance. The most critical parameter to optimize in this design is the 90Ω differential impedance.
    • The trace width and spacing to maintain the required 90Ω differential trace impedance directly at the pins of the microcontroller and directly at the ESD suppressor and USB connector is not possible to achieve. Minimize these deviations as much as possible being sure to maintain symmetry.
  • The individual traces within the differential pair needs to be length-matched to within 0.150in (3.81mm).
  • Avoid stubs when adding components to D+ and D– signals. Devices such as ESD suppressors must be located directly on the signal traces.
  • Maintain symmetry when routing differential pairs. Some PCB layout tools can assist with this kind of routing. Avoid vias if possible. If this is necessary to switch layers, then both signals in the pair pass through a via at the same distance on the trace.
  • Total trace length for the USB differential pair is limited to 12 in (30.48 cm).
  • Place ESD suppressors as close as possible to the USB connector to minimize any areas of impedance discontinuities. AM261x EVMs utilize the TPD4E02B04 ESD protection diode.
  • USB ESD Suppression - LP-AM261 Figure 8-2 USB ESD Suppression - LP-AM261
  • For best ESD and EMI performance, create a chassis ground to which the metal shield of the USB connector is connected.
  • Depending on the system design, a common mode choke can be helpful to pass EMI testing. A DLW21SN common mode choke by Murata is one recommended device, and is utilized on the AM261x EVMs. If EMI is a concern for the design, then TI recommends that a footprint for the choke be included in the design placed close to the USB connector. Figure 8-3 shows the placement of a DLW21SN choke.
  • Additional High Speed USB Platform Design Guidelines including more details on using a common mode choke can be found at USB.org.
    USB Routing Example Figure 8-3 USB Routing Example