SPRABJ8D September   2022  – May 2025 AM2612 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
      1. 2.3.1 ADC/DAC Voltage Reference Decoupling
    4. 2.4 Estimated Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2V
        2. 2.5.1.2 Digital and Analog I/O Power 3.3V
    6. 2.6 eFuse Power
  6. Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. Resets
  8. Bootstrapping
    1. 5.1 SOP Signal Implementation
  9. OSPI and QSPI Memory Implementation
    1. 6.1 ROM OSPI and QSPI Boot Requirements
      1. 6.1.1 AM263x QSPI Boot Pin Requirements
      2. 6.1.2 AM263Px OSPI and QSPI Boot Pin Requirements
      3. 6.1.3 AM261x OSPI and QSPI Boot Pin Requirements
    2. 6.2 Additional OSPI and QSPI References
  10. Debug Interfaces
    1. 7.1 JTAG Emulators and Trace
    2. 7.2 UART
  11. USB
    1. 8.1 USB Device Mode
    2. 8.2 USB Host Mode
  12. Multiplexed Peripherals
  13. 10Digital Peripherals
    1. 10.1 General Digital Peripheral Routing Guidelines
    2. 10.2 Trace Length Matching
  14. 11Analog Peripherals
    1. 11.1 General Analog Peripheral Routing Guidelines
      1. 11.1.1 Resolver ADC Routing Guidelines
  15. 12Layer Stackup
    1. 12.1 Key Stackup Features
  16. 13Vias
  17. 14BGA Power Fan-Out and Decoupling Placement
    1. 14.1 Ground Return
      1. 14.1.1 Ground Return - ZCZ Package AM26x Devices
      2. 14.1.2 Ground Return - ZNC and ZFG Package AM261x Devices
    2. 14.2 1.2V Core Digital Power
      1. 14.2.1 1.2V Core Digital Power Key Layout Considerations - ZCZ
      2. 14.2.2 1.2V Core Digital Power Key Layout Considerations - ZFG
    3. 14.3 3.3V Digital and Analog Power
      1. 14.3.1 3.3V I/O Power Key Layout Considerations - ZCZ
      2. 14.3.2 3.3V I/O Power Key Layout Considerations - ZFG
    4. 14.4 1.8V Digital and Analog Power
      1. 14.4.1 1.8V Key Layout Considerations - ZCZ
      2. 14.4.2 1.8V Key Layout Considerations - ZFG
  18. 15Summary
  19. 16References
  20. 17Revision History

Ground Return - ZCZ Package AM26x Devices

All available ground return BGA must be utilized to create the best possible electrical and thermal connection between the AM263x, AM263Px, or AM261x package and the attached PCB. Maximizing VSS BGA usage is critical from signal integrity, EMI/EMC and thermal perspectives.

Unless a separate top package heat sink is used in the design, the VSS BGA (and VDDCORE to a lesser extent) are the only heat sinking thermal connection for the BGA package. For required, thermal performance, AM26x-ZCZ PCB designs must adhere to following thermal via design requirements.

  • A minimum of 49 VSS vias in the center of the BGA must be shorted to PCB ground return planes. However, if possible, and for best thermal performance, then all VSS BGA needs to be connected to PCB ground return planes.
  • Solid ground return planes shall be used directly under the BGA on as many layers as possible.
  • Solid ground return, or the widest possible traces shall be used on the top or bottom mounting layer for VSS BGA pad connection.
  • VSS via drills shall use largest possible drill diameter. This maximizes surface area of the via, providing lowest thermal resistance.
  • VSS vias need to be conductively filled, if possible.

All of these thermal via requirements must be balanced against the necessary power and signal fan-out of the design.

The AM26x devices contain both analog and digital ground return pins. Both analog and digital ground return pins need to be shorted to a common set of ground return planes on the PCB for best noise and EMI performance as this creates the lowest possible impedance path for all return currents to follow. TI does not recommend to separate these two return paths as this typically ends up with lower performance return paths for both digital and analog signal paths.

 AM263x controlCARD Excerpt – Ground Return Vias Under AM263x BGA Layer 1 and Layer 2 Figure 14-1 AM263x controlCARD Excerpt – Ground Return Vias Under AM263x BGA Layer 1 and Layer 2
 AM263x controlCARD Excerpt – Ground Return Vias Under AM263x BGA Layer 10 Figure 14-2 AM263x controlCARD Excerpt – Ground Return Vias Under AM263x BGA Layer 10