SPRUJ66B February   2023  – September 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Key Features
        1. 1.3.1.1 Processor
        2. 1.3.1.2 Memory
        3. 1.3.1.3 JTAG Emulator
        4. 1.3.1.4 Supported Interfaces and Peripherals
        5. 1.3.1.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Revisions and Assembly Variants
    2. 2.2 System Description
      1. 2.2.1 Board Image With Markings
      2. 2.2.2 Functional Block Diagram
      3. 2.2.3 AM62A Low Power SK EVM Interface Mapping
      4. 2.2.4 Power ON/OFF Procedures
        1. 2.2.4.1 Power-On Procedure
        2. 2.2.4.2 Power-Off Procedure
        3. 2.2.4.3 Power Test Points
      5. 2.2.5 Peripheral and Major Component Description
        1. 2.2.5.1  Clocking
          1. 2.2.5.1.1 Peripheral Ref Clock
        2. 2.2.5.2  Reset
        3. 2.2.5.3  CSI Interface
        4. 2.2.5.4  Audio Codec Interface
        5. 2.2.5.5  HDMI Display Interface
        6. 2.2.5.6  JTAG Interface
        7. 2.2.5.7  Test Automation Header
        8. 2.2.5.8  UART Interface
        9. 2.2.5.9  USB Interface
          1. 2.2.5.9.1 USB 2 0 Type A Interface
          2. 2.2.5.9.2 USB 2 0 Type C Interface
        10. 2.2.5.10 Memory Interfaces
          1. 2.2.5.10.1 LPDDR4 Interface
          2. 2.2.5.10.2 Octal Serial Peripheral Interface (OSPI)
          3. 2.2.5.10.3 MMC Interfaces
            1. 2.2.5.10.3.1 MMC0 - eMMC Interface
            2. 2.2.5.10.3.2 MMC1 - Micro SD Interface
            3. 2.2.5.10.3.3 MMC2 - M.2 Key E Interface
          4. 2.2.5.10.4 Board ID EEPROM
        11. 2.2.5.11 Ethernet Interface
          1. 2.2.5.11.1 CPSW Ethernet PHY Default Configuration
        12. 2.2.5.12 GPIO Port Expander
        13. 2.2.5.13 GPIO Mapping
        14. 2.2.5.14 Power
          1. 2.2.5.14.1 Power Requirements
          2. 2.2.5.14.2 Power Input
          3. 2.2.5.14.3 Power Supply
          4. 2.2.5.14.4 AM62A SoC Power
          5. 2.2.5.14.5 Current Monitoring
        15. 2.2.5.15 AM62A Low Power SK EVM User Setup and Configuration
          1. 2.2.5.15.1 Boot Modes
          2. 2.2.5.15.2 User Test LEDs
        16. 2.2.5.16 Expansion Headers
          1. 2.2.5.16.1 User Expansion Connector
          2. 2.2.5.16.2 MCU Connector
        17. 2.2.5.17 I2C Address Mapping
  9. 3Hardware Design Files
    1. 3.1 Schematics, PCB Layout and BOM
  10. 4Additional Information
    1. 4.1 Known Hardware or Software Issues
    2. 4.2 EMC, EMI, and ESD Compliance
    3. 4.3 Trademarks
    4.     72
  11. 5Revision History
2.2.5.16.2 MCU Connector

AM62A Low Power SK EVM has a 14 x 2 standard 0.1” spaced MCU connector which includes signals connected to the MCU Domain of the SOC. The connected signals include MCU_I2C0, MCU_UART0 (with flow control), MCU_SPI0 and MCU_MCAN0 signals. Additional control signals connected on the Header includes CONN_MCU_RESETz, CONN_MCU_PORz, MCU_RESETSTATz, MCU_SAFETY_ERRORn, 3.3V IO supply and GND. MCU_UART0 signals from AM62A SOC are connected to both MCU Header and FT4232 Bridge through a MUX Mfr Part # SN74CB3Q3257PWR. The MCU Header does not include the Board ID memory interface. Allowed current limit is 100mA on 3.3V rail.

SK-AM62A-LP MCU Connector Interface Figure 2-32 MCU Connector Interface
Table 2-36 MCU Table Connector
Pin No. SoCBall No. Netname
1 - VCC_3V3_SYS
2 - DGND
3 - DGND
4 B12 MCU_SPI0_D1
5 D7 CAN_FD_WKUP_HDR_INH
6 A15 MCU_SPI0_D0
7 - DGND
8 C11 MCU_SPI0_CS1
9 - DGND
10 D7 MCU_GPIO0_15
11 B9 MCU_GPIO0_16
12 B11 MCU_UART0_CTS_CONN
13 D8 MCU_UART0_RXD_CONN
14 - DGND
15 - DGND
16 C7 MCU_MCAN0_TX
17 D10 MCU_UART0_RTS_CONN
18 B13 MCU_SPI0_CLK
19 F8 MCU_UART0_TXD_CONN
20 - DGND
21 D9 MCU_I2C0_SDA
22 E8 MCU_MCAN0_RX
23 D14 MCU_RESETSTATz
24 E12 MCU_I2C0_SCL
25 C12 CONN_MCU_RESETz
26 B8 MCU_SAFETY_ERRORz_3V3
27 - DGND
28 A7 CONN_MCU_PORz